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[/] [t48/] [tags/] [rel_1_1] - Rev 150

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Rev Log message Author Age Path
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7193d 19h /t48/tags/rel_1_1
149 update arniml 7193d 19h /t48/tags/rel_1_1
148 initial check-in arniml 7193d 19h /t48/tags/rel_1_1
147 initial check-in for release 0.5 BETA arniml 7229d 21h /t48/tags/rel_1_1
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7230d 21h /t48/tags/rel_1_1
145 remove PROG and end of XTAL2, see comment for details arniml 7230d 22h /t48/tags/rel_1_1
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7230d 22h /t48/tags/rel_1_1
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7230d 23h /t48/tags/rel_1_1
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7230d 23h /t48/tags/rel_1_1
141 disable external memory to avoid conflicts with outl a, bus arniml 7230d 23h /t48/tags/rel_1_1
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7230d 23h /t48/tags/rel_1_1
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7232d 09h /t48/tags/rel_1_1
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7232d 09h /t48/tags/rel_1_1
137 add link to COMPILE_LIST arniml 7269d 22h /t48/tags/rel_1_1
136 initial check-in arniml 7269d 22h /t48/tags/rel_1_1
135 add bug
PSENn Timing		 arniml 7274d 08h /t48/tags/rel_1_1
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7274d 18h /t48/tags/rel_1_1
133 add checks for PSEN arniml 7274d 18h /t48/tags/rel_1_1
132 stop simulation upon assertion error arniml 7274d 18h /t48/tags/rel_1_1
131 update arniml 7274d 18h /t48/tags/rel_1_1
130 initial check-in arniml 7274d 18h /t48/tags/rel_1_1
129 cleanup copyright notice arniml 7337d 01h /t48/tags/rel_1_1
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7344d 05h /t48/tags/rel_1_1
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7344d 06h /t48/tags/rel_1_1
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7344d 06h /t48/tags/rel_1_1
125 exclude from dump compare arniml 7344d 06h /t48/tags/rel_1_1
124 fix wrong handling of MB after return from interrupt arniml 7345d 04h /t48/tags/rel_1_1
123 support hex file for external ROM arniml 7345d 04h /t48/tags/rel_1_1
122 test MB after return from interrupt arniml 7345d 04h /t48/tags/rel_1_1
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7347d 21h /t48/tags/rel_1_1

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