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[/] [t48/] [tags/] [rel_1_1] - Rev 181

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Rev Log message Author Age Path
181 fix typo arniml 6993d 16h /t48/tags/rel_1_1
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7001d 22h /t48/tags/rel_1_1
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7001d 22h /t48/tags/rel_1_1
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7003d 10h /t48/tags/rel_1_1
177 Implement db_dir_o glitch-safe arniml 7003d 10h /t48/tags/rel_1_1
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7003d 10h /t48/tags/rel_1_1
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 13h /t48/tags/rel_1_1
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 13h /t48/tags/rel_1_1
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 13h /t48/tags/rel_1_1
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7033d 10h /t48/tags/rel_1_1
171 remove obsolete output stack_high_o arniml 7034d 10h /t48/tags/rel_1_1
170 intermediate update arniml 7035d 16h /t48/tags/rel_1_1
169 initial check-in arniml 7035d 22h /t48/tags/rel_1_1
168 change address range of wb_master arniml 7035d 22h /t48/tags/rel_1_1
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7035d 22h /t48/tags/rel_1_1
166 assign default for state_s arniml 7037d 13h /t48/tags/rel_1_1
165 add component wb_master.vhd arniml 7038d 12h /t48/tags/rel_1_1
164 initial check-in arniml 7038d 12h /t48/tags/rel_1_1
163 add bug
Wrong clock applied to T0		 arniml 7039d 12h /t48/tags/rel_1_1
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7039d 12h /t48/tags/rel_1_1
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7070d 16h /t48/tags/rel_1_1
160 add others to case statement arniml 7191d 12h /t48/tags/rel_1_1
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7191d 12h /t48/tags/rel_1_1
158 added hierarchies t8039_notri and t8048_notri arniml 7191d 12h /t48/tags/rel_1_1
157 removed obsolete constant arniml 7191d 12h /t48/tags/rel_1_1
156 added hierarchy t8039_notri arniml 7191d 12h /t48/tags/rel_1_1
155 initial check-in arniml 7191d 12h /t48/tags/rel_1_1
154 added t8039_notri hierarchy arniml 7191d 13h /t48/tags/rel_1_1
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7192d 10h /t48/tags/rel_1_1
152 added hierarchy t8048_notri and system components package arniml 7193d 01h /t48/tags/rel_1_1

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