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[/] [t48/] [tags/] [rel_1_1] - Rev 77

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Rev Log message Author Age Path
77 move from std_logic_arith to numeric_std arniml 7416d 11h /t48/tags/rel_1_1
76 initial check-in arniml 7416d 15h /t48/tags/rel_1_1
75 remove obsolete design unit arniml 7416d 15h /t48/tags/rel_1_1
74 enhance pass/fail detection arniml 7417d 00h /t48/tags/rel_1_1
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7417d 00h /t48/tags/rel_1_1
72 removed superfluous signal from sensitivity list arniml 7417d 00h /t48/tags/rel_1_1
71 add T8039 and its testbench arniml 7422d 16h /t48/tags/rel_1_1
70 clean test cell before make arniml 7422d 16h /t48/tags/rel_1_1
69 fix name of istrobe arniml 7422d 16h /t48/tags/rel_1_1
68 connect T0 and T1 to P1 arniml 7422d 16h /t48/tags/rel_1_1
67 initial check-in arniml 7422d 16h /t48/tags/rel_1_1
66 add temporary workaround for GHDL 0.11 arniml 7422d 16h /t48/tags/rel_1_1
65 clean up sensitivity list arniml 7422d 16h /t48/tags/rel_1_1
64 + enhance instruction strobe generation
+ rework address output under EA=1 conditions		 arniml 7422d 16h /t48/tags/rel_1_1
63 reset machine state to MSTATE3 to allow proper instruction fetch
after reset		 arniml 7422d 16h /t48/tags/rel_1_1
62 initial check-in arniml 7422d 16h /t48/tags/rel_1_1
61 expand script for dump compare arniml 7424d 13h /t48/tags/rel_1_1
60 + add marker for injected calls
+ suppress intstruction strobes for injected calls		 arniml 7425d 13h /t48/tags/rel_1_1
59 increment prescaler with MSTATE4 arniml 7425d 13h /t48/tags/rel_1_1
58 add periodic interrupt arniml 7425d 13h /t48/tags/rel_1_1
57 abort if no interrupt occurs arniml 7425d 13h /t48/tags/rel_1_1
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7426d 14h /t48/tags/rel_1_1
55 add dependency to tb_behav_pack for decoder arniml 7426d 14h /t48/tags/rel_1_1
54 - add tb_istrobe_s arniml 7426d 14h /t48/tags/rel_1_1
53 make istrobe visible through testbench package arniml 7426d 14h /t48/tags/rel_1_1
52 + fix bug in PSW[3]
+ read SP properly for dump		 arniml 7426d 14h /t48/tags/rel_1_1
51 + implement Port1 and Port2
+ connect T0 and T1
+ return proper program memory contents		 arniml 7426d 14h /t48/tags/rel_1_1
49 Imported sources arniml 7431d 16h /t48/tags/rel_1_1
48 update copyright notice arniml 7431d 16h /t48/tags/rel_1_1
47 initial check-in arniml 7431d 16h /t48/tags/rel_1_1

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