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[/] [t48/] [tags/] [rel_1_4] - Rev 107

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Rev Log message Author Age Path
107 tie EA to '1' arniml 7359d 00h /t48/tags/rel_1_4
106 clean-up use of ea_i arniml 7359d 00h /t48/tags/rel_1_4
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7361d 10h /t48/tags/rel_1_4
104 add white_box directory to test suite arniml 7362d 07h /t48/tags/rel_1_4
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7362d 07h /t48/tags/rel_1_4
102 update for changes in address space of external memory arniml 7362d 07h /t48/tags/rel_1_4
101 assert p2_read_p2_o when expander port is read arniml 7362d 07h /t48/tags/rel_1_4
100 reorder data_o generation arniml 7362d 07h /t48/tags/rel_1_4
99 initial check-in arniml 7362d 07h /t48/tags/rel_1_4
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7362d 08h /t48/tags/rel_1_4
97 initial check-in arniml 7362d 08h /t48/tags/rel_1_4
96 select dedicated directorie(s) for regression arniml 7363d 06h /t48/tags/rel_1_4
95 check counter inactivity arniml 7363d 06h /t48/tags/rel_1_4
94 initial check-in arniml 7363d 06h /t48/tags/rel_1_4
93 add support for line coverage evaluation with gcov arniml 7363d 06h /t48/tags/rel_1_4
92 work around bug in Quartus II 4.0 arniml 7363d 06h /t48/tags/rel_1_4
91 fix edge detector bug for counter arniml 7363d 06h /t48/tags/rel_1_4
90 intial check-in arniml 7363d 06h /t48/tags/rel_1_4
89 initial check-in arniml 7377d 03h /t48/tags/rel_1_4
88 allow memory bank switching during interrupts arniml 7378d 05h /t48/tags/rel_1_4
87 abort gracfullt if memory bank switching does not work arniml 7378d 05h /t48/tags/rel_1_4
86 update notice about expander port instructions arniml 7378d 10h /t48/tags/rel_1_4
85 initial check-in arniml 7378d 10h /t48/tags/rel_1_4
84 add if_timing module arniml 7384d 01h /t48/tags/rel_1_4
83 connect if_timing to P2 output of T48 arniml 7384d 01h /t48/tags/rel_1_4
82 check expander timings arniml 7384d 01h /t48/tags/rel_1_4
81 initial check-in arniml 7384d 06h /t48/tags/rel_1_4
80 added if_timing arniml 7384d 06h /t48/tags/rel_1_4
79 add if_timing module arniml 7384d 06h /t48/tags/rel_1_4
78 adjust external timing of BUS arniml 7384d 06h /t48/tags/rel_1_4

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