OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 118

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7318d 01h /t48/tags/rel_1_4
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7319d 02h /t48/tags/rel_1_4
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7347d 02h /t48/tags/rel_1_4
115 extend description arniml 7348d 06h /t48/tags/rel_1_4
114 initial check-in arniml 7352d 02h /t48/tags/rel_1_4
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7358d 11h /t48/tags/rel_1_4
112 update tb_behav_c0 for new ROM layout arniml 7358d 11h /t48/tags/rel_1_4
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7358d 11h /t48/tags/rel_1_4
110 exchange syn_rom for lpm_rom arniml 7358d 11h /t48/tags/rel_1_4
109 add new bug for release 0.1 BETA arniml 7359d 01h /t48/tags/rel_1_4
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7359d 01h /t48/tags/rel_1_4
107 tie EA to '1' arniml 7359d 01h /t48/tags/rel_1_4
106 clean-up use of ea_i arniml 7359d 01h /t48/tags/rel_1_4
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7361d 10h /t48/tags/rel_1_4
104 add white_box directory to test suite arniml 7362d 08h /t48/tags/rel_1_4
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7362d 08h /t48/tags/rel_1_4
102 update for changes in address space of external memory arniml 7362d 08h /t48/tags/rel_1_4
101 assert p2_read_p2_o when expander port is read arniml 7362d 08h /t48/tags/rel_1_4
100 reorder data_o generation arniml 7362d 08h /t48/tags/rel_1_4
99 initial check-in arniml 7362d 08h /t48/tags/rel_1_4
98 Fix bug "ANL and ORL to P1/P2 read port status instead of port output register" arniml 7362d 09h /t48/tags/rel_1_4
97 initial check-in arniml 7362d 09h /t48/tags/rel_1_4
96 select dedicated directorie(s) for regression arniml 7363d 06h /t48/tags/rel_1_4
95 check counter inactivity arniml 7363d 06h /t48/tags/rel_1_4
94 initial check-in arniml 7363d 06h /t48/tags/rel_1_4
93 add support for line coverage evaluation with gcov arniml 7363d 07h /t48/tags/rel_1_4
92 work around bug in Quartus II 4.0 arniml 7363d 07h /t48/tags/rel_1_4
91 fix edge detector bug for counter arniml 7363d 07h /t48/tags/rel_1_4
90 intial check-in arniml 7363d 07h /t48/tags/rel_1_4
89 initial check-in arniml 7377d 03h /t48/tags/rel_1_4

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.