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[/] [t48/] [tags/] [rel_1_4] - Rev 132

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Rev Log message Author Age Path
132 stop simulation upon assertion error arniml 7246d 07h /t48/tags/rel_1_4
131 update arniml 7246d 07h /t48/tags/rel_1_4
130 initial check-in arniml 7246d 07h /t48/tags/rel_1_4
129 cleanup copyright notice arniml 7308d 15h /t48/tags/rel_1_4
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7315d 18h /t48/tags/rel_1_4
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7315d 19h /t48/tags/rel_1_4
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7315d 19h /t48/tags/rel_1_4
125 exclude from dump compare arniml 7315d 19h /t48/tags/rel_1_4
124 fix wrong handling of MB after return from interrupt arniml 7316d 17h /t48/tags/rel_1_4
123 support hex file for external ROM arniml 7316d 17h /t48/tags/rel_1_4
122 test MB after return from interrupt arniml 7316d 17h /t48/tags/rel_1_4
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7319d 10h /t48/tags/rel_1_4
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7319d 10h /t48/tags/rel_1_4
119 add int_in_progress_o to entity of int module arniml 7319d 10h /t48/tags/rel_1_4
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7319d 10h /t48/tags/rel_1_4
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7320d 11h /t48/tags/rel_1_4
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7348d 11h /t48/tags/rel_1_4
115 extend description arniml 7349d 15h /t48/tags/rel_1_4
114 initial check-in arniml 7353d 11h /t48/tags/rel_1_4
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7359d 20h /t48/tags/rel_1_4
112 update tb_behav_c0 for new ROM layout arniml 7359d 20h /t48/tags/rel_1_4
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7359d 20h /t48/tags/rel_1_4
110 exchange syn_rom for lpm_rom arniml 7359d 20h /t48/tags/rel_1_4
109 add new bug for release 0.1 BETA arniml 7360d 09h /t48/tags/rel_1_4
108 Fix for:
External Program Memory ignored when EA = 0		 arniml 7360d 10h /t48/tags/rel_1_4
107 tie EA to '1' arniml 7360d 10h /t48/tags/rel_1_4
106 clean-up use of ea_i arniml 7360d 10h /t48/tags/rel_1_4
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7362d 19h /t48/tags/rel_1_4
104 add white_box directory to test suite arniml 7363d 17h /t48/tags/rel_1_4
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7363d 17h /t48/tags/rel_1_4

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