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[/] [t48/] [tags/] [rel_1_4] - Rev 143

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143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7202d 13h /t48/tags/rel_1_4
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7202d 13h /t48/tags/rel_1_4
141 disable external memory to avoid conflicts with outl a, bus arniml 7202d 13h /t48/tags/rel_1_4
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7202d 13h /t48/tags/rel_1_4
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7203d 23h /t48/tags/rel_1_4
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7203d 23h /t48/tags/rel_1_4
137 add link to COMPILE_LIST arniml 7241d 11h /t48/tags/rel_1_4
136 initial check-in arniml 7241d 11h /t48/tags/rel_1_4
135 add bug
PSENn Timing		 arniml 7245d 22h /t48/tags/rel_1_4
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7246d 08h /t48/tags/rel_1_4
133 add checks for PSEN arniml 7246d 08h /t48/tags/rel_1_4
132 stop simulation upon assertion error arniml 7246d 08h /t48/tags/rel_1_4
131 update arniml 7246d 08h /t48/tags/rel_1_4
130 initial check-in arniml 7246d 08h /t48/tags/rel_1_4
129 cleanup copyright notice arniml 7308d 15h /t48/tags/rel_1_4
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7315d 19h /t48/tags/rel_1_4
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7315d 20h /t48/tags/rel_1_4
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7315d 20h /t48/tags/rel_1_4
125 exclude from dump compare arniml 7315d 20h /t48/tags/rel_1_4
124 fix wrong handling of MB after return from interrupt arniml 7316d 18h /t48/tags/rel_1_4
123 support hex file for external ROM arniml 7316d 18h /t48/tags/rel_1_4
122 test MB after return from interrupt arniml 7316d 18h /t48/tags/rel_1_4
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7319d 11h /t48/tags/rel_1_4
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7319d 11h /t48/tags/rel_1_4
119 add int_in_progress_o to entity of int module arniml 7319d 11h /t48/tags/rel_1_4
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7319d 11h /t48/tags/rel_1_4
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7320d 11h /t48/tags/rel_1_4
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7348d 12h /t48/tags/rel_1_4
115 extend description arniml 7349d 16h /t48/tags/rel_1_4
114 initial check-in arniml 7353d 12h /t48/tags/rel_1_4

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