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[/] [t48/] [tags/] [rel_1_4] - Rev 174

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Rev Log message Author Age Path
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 18h /t48/tags/rel_1_4
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 18h /t48/tags/rel_1_4
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7004d 14h /t48/tags/rel_1_4
171 remove obsolete output stack_high_o arniml 7005d 15h /t48/tags/rel_1_4
170 intermediate update arniml 7006d 21h /t48/tags/rel_1_4
169 initial check-in arniml 7007d 02h /t48/tags/rel_1_4
168 change address range of wb_master arniml 7007d 02h /t48/tags/rel_1_4
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7007d 02h /t48/tags/rel_1_4
166 assign default for state_s arniml 7008d 18h /t48/tags/rel_1_4
165 add component wb_master.vhd arniml 7009d 17h /t48/tags/rel_1_4
164 initial check-in arniml 7009d 17h /t48/tags/rel_1_4
163 add bug
Wrong clock applied to T0		 arniml 7010d 17h /t48/tags/rel_1_4
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7010d 17h /t48/tags/rel_1_4
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7041d 21h /t48/tags/rel_1_4
160 add others to case statement arniml 7162d 17h /t48/tags/rel_1_4
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7162d 17h /t48/tags/rel_1_4
158 added hierarchies t8039_notri and t8048_notri arniml 7162d 17h /t48/tags/rel_1_4
157 removed obsolete constant arniml 7162d 17h /t48/tags/rel_1_4
156 added hierarchy t8039_notri arniml 7162d 17h /t48/tags/rel_1_4
155 initial check-in arniml 7162d 17h /t48/tags/rel_1_4
154 added t8039_notri hierarchy arniml 7162d 17h /t48/tags/rel_1_4
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7163d 15h /t48/tags/rel_1_4
152 added hierarchy t8048_notri and system components package arniml 7164d 06h /t48/tags/rel_1_4
151 added hierarchy t8048_notri and components package for t48 systems arniml 7164d 06h /t48/tags/rel_1_4
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7164d 14h /t48/tags/rel_1_4
149 update arniml 7164d 14h /t48/tags/rel_1_4
148 initial check-in arniml 7164d 14h /t48/tags/rel_1_4
147 initial check-in for release 0.5 BETA arniml 7200d 15h /t48/tags/rel_1_4
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7201d 15h /t48/tags/rel_1_4
145 remove PROG and end of XTAL2, see comment for details arniml 7201d 17h /t48/tags/rel_1_4

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