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[/] [t48/] [tags/] [rel_1_4] - Rev 192

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Rev Log message Author Age Path
192 update list for Wishbone toplevel arniml 6909d 18h /t48/tags/rel_1_4
191 preliminary version 0.2 arniml 6909d 21h /t48/tags/rel_1_4
190 finalize change log for release 0.6 beta arniml 6910d 16h /t48/tags/rel_1_4
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6941d 18h /t48/tags/rel_1_4
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6941d 18h /t48/tags/rel_1_4
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6941d 18h /t48/tags/rel_1_4
186 update to version 0.2 arniml 6942d 20h /t48/tags/rel_1_4
185 initial check-in arniml 6947d 18h /t48/tags/rel_1_4
184 initial check-in arniml 6947d 19h /t48/tags/rel_1_4
183 fix missing assignment to outclock arniml 6947d 22h /t48/tags/rel_1_4
182 intermediate version arniml 7027d 20h /t48/tags/rel_1_4
181 fix typo arniml 7027d 23h /t48/tags/rel_1_4
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7036d 05h /t48/tags/rel_1_4
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7036d 05h /t48/tags/rel_1_4
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7037d 17h /t48/tags/rel_1_4
177 Implement db_dir_o glitch-safe arniml 7037d 17h /t48/tags/rel_1_4
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7037d 17h /t48/tags/rel_1_4
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7038d 20h /t48/tags/rel_1_4
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7038d 20h /t48/tags/rel_1_4
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7038d 20h /t48/tags/rel_1_4
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7067d 17h /t48/tags/rel_1_4
171 remove obsolete output stack_high_o arniml 7068d 17h /t48/tags/rel_1_4
170 intermediate update arniml 7069d 23h /t48/tags/rel_1_4
169 initial check-in arniml 7070d 05h /t48/tags/rel_1_4
168 change address range of wb_master arniml 7070d 05h /t48/tags/rel_1_4
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7070d 05h /t48/tags/rel_1_4
166 assign default for state_s arniml 7071d 20h /t48/tags/rel_1_4
165 add component wb_master.vhd arniml 7072d 19h /t48/tags/rel_1_4
164 initial check-in arniml 7072d 19h /t48/tags/rel_1_4
163 add bug
Wrong clock applied to T0		 arniml 7073d 19h /t48/tags/rel_1_4

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