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[/] [t48/] [tags/] [rel_1_4] - Rev 201

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Rev Log message Author Age Path
201 split low impedance markers for P2 arniml 6858d 00h /t48/tags/rel_1_4
200 add check for
tCP: Port Control Setup to PROG'		 arniml 6858d 00h /t48/tags/rel_1_4
199 initial check-in arniml 6858d 01h /t48/tags/rel_1_4
198 fix package dependencies arniml 6858d 05h /t48/tags/rel_1_4
197 preliminary version 0.3 arniml 6859d 08h /t48/tags/rel_1_4
196 update to version 0.3 arniml 6859d 08h /t48/tags/rel_1_4
195 Suppress assertion of bus_read_bus_s when interrupt is pending.
This should fix bug report
"PROBLEM WHEN INT AND JMP"		 arniml 6859d 12h /t48/tags/rel_1_4
194 initial check-in arniml 6859d 12h /t48/tags/rel_1_4
193 iManual arniml 6874d 14h /t48/tags/rel_1_4
192 update list for Wishbone toplevel arniml 6875d 00h /t48/tags/rel_1_4
191 preliminary version 0.2 arniml 6875d 04h /t48/tags/rel_1_4
190 finalize change log for release 0.6 beta arniml 6875d 22h /t48/tags/rel_1_4
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"		 arniml 6907d 00h /t48/tags/rel_1_4
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6907d 01h /t48/tags/rel_1_4
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6907d 01h /t48/tags/rel_1_4
186 update to version 0.2 arniml 6908d 02h /t48/tags/rel_1_4
185 initial check-in arniml 6913d 00h /t48/tags/rel_1_4
184 initial check-in arniml 6913d 01h /t48/tags/rel_1_4
183 fix missing assignment to outclock arniml 6913d 04h /t48/tags/rel_1_4
182 intermediate version arniml 6993d 03h /t48/tags/rel_1_4
181 fix typo arniml 6993d 06h /t48/tags/rel_1_4
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7001d 11h /t48/tags/rel_1_4
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7001d 12h /t48/tags/rel_1_4
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7002d 23h /t48/tags/rel_1_4
177 Implement db_dir_o glitch-safe arniml 7002d 23h /t48/tags/rel_1_4
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7002d 23h /t48/tags/rel_1_4
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 02h /t48/tags/rel_1_4
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 02h /t48/tags/rel_1_4
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7004d 03h /t48/tags/rel_1_4
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7032d 23h /t48/tags/rel_1_4

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