OpenCores
URL https://opencores.org/ocsvn/t51/t51/trunk

Subversion Repositories t51

[/] [t51/] [trunk] - Rev 51

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
51 New directory structure. root 5567d 21h /t51/trunk
50 initial version andreas 6267d 09h /trunk
49 some improvements andreas 6430d 19h /trunk
48 *** empty log message *** andreas 6599d 09h /trunk
47 updated t8052 core andreas 6599d 15h /trunk
46 some updates andreas 6599d 15h /trunk
45 *** empty log message *** andreas 6599d 15h /trunk
44 some updates and bugfixes andreas 6599d 15h /trunk
43 bugfix for interrupts at stalled instructions andreas 6682d 09h /trunk
42 *** empty log message *** andreas 6701d 08h /trunk
41 some updates andreas 6701d 08h /trunk
40 *** empty log message *** andreas 6701d 08h /trunk
39 some updates for T8032 andreas 6701d 08h /trunk
38 some updates andreas 6710d 15h /trunk
37 some updates andreas 6710d 15h /trunk
36 some updates andreas 6710d 19h /trunk
35 some updates andreas 6710d 19h /trunk
34 bugfix for mode 0 andreas 6719d 11h /trunk
33 bugfix for JBC instruction andreas 6731d 16h /trunk
32 bugfix for two subsequent movx instructions andreas 6768d 11h /trunk
31 update andreas 6854d 10h /trunk
30 Made some bugfixes andreas 6855d 13h /trunk
29 Removed UNISIM library jesus 7865d 17h /trunk
28 Added -n option and component declaration jesus 7893d 14h /trunk
27 Added Leonardo .ucf generation jesus 7893d 14h /trunk
26 Updated for ISE 5.1 jesus 7900d 10h /trunk
25 Fixed typo jesus 7910d 02h /trunk
24 Fixed for ISE 5.1 jesus 7910d 02h /trunk
23 Xilinx SSRAM, initial release jesus 7920d 04h /trunk
22 Removed write through jesus 7948d 01h /trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.