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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 221

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186 Testbench has a lot of new tests. gabrieloshiro 5606d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5606d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
183 STA, STY and STX should be working now gabrieloshiro 5607d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5607d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
179 STA, STY and STX fixed gabrieloshiro 5607d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
178 STA, STY and STX fixed gabrieloshiro 5607d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
176 RTI works for me gabrieloshiro 5607d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5608d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5608d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5608d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
172 RTI supported to be compatible with stella gabrieloshiro 5608d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
171 Removed debug messages. creep 5608d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
169 ADC bugs finally fixed. gabrieloshiro 5609d 04h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5609d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
167 Now SBC is supposed to work. gabrieloshiro 5609d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
166 Commiting again! gabrieloshiro 5609d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
165 SBC and PHP fixed! gabrieloshiro 5609d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5609d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
163 Still having bugs on ADC with decimal flag! Is it correct now? gabrieloshiro 5609d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
162 ADC with decimal mode ON, bug fixed! gabrieloshiro 5609d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5609d 09h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5612d 05h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
157 gabrieloshiro 5612d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5612d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5612d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
152 Bug #24 from trac was fixed. gabrieloshiro 5613d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151 tah comitado! gabrieloshiro 5613d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5613d 06h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5613d 07h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5613d 08h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

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