OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Rev 224

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
224 Added a top level for the tests. creep 5545d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
186 Testbench has a lot of new tests. gabrieloshiro 5578d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5578d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
183 STA, STY and STX should be working now gabrieloshiro 5579d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5579d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
179 STA, STY and STX fixed gabrieloshiro 5579d 17h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
178 STA, STY and STX fixed gabrieloshiro 5579d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
176 RTI works for me gabrieloshiro 5579d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5580d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5580d 17h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
169 ADC bugs finally fixed. gabrieloshiro 5581d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
165 SBC and PHP fixed! gabrieloshiro 5581d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5581d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5581d 17h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5584d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5584d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5585d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5585d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5585d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5586d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
143 Modified the inputs so the alu resets. creep 5586d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
140 Variable names were changed according to coding guidelines. gabrieloshiro 5586d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
136 Some minor coding style changes. gabrieloshiro 5587d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5591d 19h /t6507lp/trunk/rtl/verilog/T6507LP_ALU_TestBench.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.