OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 128

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5620d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 5622d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 5622d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 5622d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 5622d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 5623d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5623d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109 PLA and PLP are coded and simulated. creep 5623d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108 PHA and PHP are coded and simulated. creep 5623d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 5623d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 5623d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 5623d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 5624d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 5624d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 5624d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5624d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5627d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5627d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5628d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5628d 22h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5629d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86 Zero page indexed mode is working fine. creep 5629d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5629d 22h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5630d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78 ZPG coded and simulated. creep 5630d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77 ZPG coded. Simulation is halfway. creep 5630d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5630d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5634d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
68 The FSM module is now parametrized.
Also, several changes were made to remove most of the lint warnings.		 creep 5634d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
63 Fixed several HAL warnings. Still plenty to do. creep 5635d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.