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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 243

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Rev Log message Author Age Path
243 Fixing STA_IDY bug creep 5530d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
242 Bug regardind the STA_IDY opcode creep 5530d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
212 Bug #56: ZPX page crossing. creep 5556d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
205 Bug #51: NOP shouldnt feed the ALU with enable 1'b1. creep 5559d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
202 Bug #49: RTI and RTS behavior was recoded. creep 5562d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
200 Bug #48: SP wrong after decrement. creep 5562d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
199 Fixed two warning messages at the FSM. creep 5562d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
196 Syncing both repositories. creep 5563d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
195 FSM was locking on TSX/TXS. creep 5563d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
194 Fixing bug #45 creep 5563d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
146 Fixed ticket #13: reset behavior in the FSM. creep 5585d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
128 $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized. gabrieloshiro 5590d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
120 Added some extra commentaries. creep 5592d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
117 Fixed the top level and connected the entire project. creep 5592d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
115 Renamed the signal control. It is mem_rw now. creep 5592d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
112 Created a global timescale file for the project. creep 5592d 22h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
111 Performed some linting after coding was finished. creep 5593d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
110 All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage. creep 5593d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
109 PLA and PLP are coded and simulated. creep 5593d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108 PHA and PHP are coded and simulated. creep 5593d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 5593d 18h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 5593d 19h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 5593d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 5594d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 5594d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 5594d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5594d 22h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5597d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5597d 17h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5598d 14h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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