| Rev |
Log message |
Author |
Age |
Path |
| 25 |
Wait for memory state now works as expected, and opcode `mov [reg], immd` works now |
earlz |
4456d 13h |
/tinycpu |
| 24 |
Good news, mov to IP actually works as expected! |
earlz |
4457d 07h |
/tinycpu |
| 23 |
Added top module for testing how our memory and cpu will work together. (hint: success)
Messing around with a small timing issue in core |
earlz |
4457d 07h |
/tinycpu |
| 22 |
Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch |
earlz |
4457d 23h |
/tinycpu |
| 21 |
The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it. |
earlz |
4457d 23h |
/tinycpu |
| 20 |
fuck it. All sorts of broken, will try to fix it tomorrow |
earlz |
4458d 23h |
/tinycpu |
| 19 |
Got beginning of core/decoder for the CPU |
earlz |
4459d 00h |
/tinycpu |
| 18 |
Finished memory controller |
earlz |
4462d 10h |
/tinycpu |
| 17 |
Added fetch component for fetching from memory to instruction register
Added additional testing for carryover to make sure it's correct |
earlz |
4463d 00h |
/tinycpu |
| 16 |
Renamed incdec to carryover (see design for why).
carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding. |
earlz |
4466d 02h |
/tinycpu |
| 15 |
Added README, LICENSE, and the (so far not created) incdec component |
earlz |
4467d 23h |
/tinycpu |
| 14 |
Added ALU with all the operations we'll need. Synthesizes as well trivially |
earlz |
4468d 08h |
/tinycpu |
| 13 |
Forgot about the new library I added |
earlz |
4468d 10h |
/tinycpu |
| 12 |
registerfile has ports for every register now
makefile now uses GHW file format for gtkwave instead of VCD |
earlz |
4468d 11h |
/tinycpu |
| 11 |
Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge |
earlz |
4472d 00h |
/tinycpu |
| 10 |
Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs |
earlz |
4472d 01h |
/tinycpu |
| 9 |
Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench |
earlz |
4472d 08h |
/tinycpu |
| 8 |
Added blockram for inferring actual block RAM.
Now we need a memory controller, not a crappy memory emulation thing |
earlz |
4473d 08h |
/tinycpu |
| 7 |
Changed memory to fix bound check error
Decreased size of RAM since 4096 bytes of RAM would require an FPGA with more than 32K flip-flops (mine has ~4000) |
earlz |
4473d 09h |
/tinycpu |
| 6 |
Reworked memory code to hopefully synthesize better |
earlz |
4473d 14h |
/tinycpu |
| 5 |
Modified registerfile to be dual-port for both read and write |
earlz |
4474d 01h |
/tinycpu |
| 4 |
Added internal memory interface
Updated design |
earlz |
4474d 09h |
/tinycpu |
| 3 |
Updated registerfile to have 2 read ports
Added super rough design document mainly just for brainstorming |
earlz |
4475d 01h |
/tinycpu |
| 2 |
Initial commit |
earlz |
4475d 02h |
/tinycpu |
| 1 |
The project and the structure was created |
root |
4475d 04h |
/tinycpu |
