OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk] - Rev 68

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.		 ghutchis 7076d 06h /tv80/trunk
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.		 ghutchis 7076d 06h /tv80/trunk
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7076d 06h /tv80/trunk
65 Major restructuring of simple_gmii block.

1) Changed simple_gmii block to simple_gmii_core
2) Migrated RAM instances out of core into top level
3) Removed CPU interface logic and created CPU interface block using
register generator
4) Changed status register to interrupt register and added interrupt
logic		 ghutchis 7076d 06h /tv80/trunk
64 Created rgen script and expanded available register types ghutchis 7077d 05h /tv80/trunk
63 Added simple regression script. -r command runs all tests (serially),
-c command checks results after all tests have completed.		 ghutchis 7111d 09h /tv80/trunk
62 Reset timeout counter whenever a message is printed ghutchis 7111d 09h /tv80/trunk
61 Added timeout disable for large buf sizes ghutchis 7111d 09h /tv80/trunk
60 Added ifdef TV80_REFRESH, to remove refresh logic by default. Also
ran untabify to remove tabs from source code.		 ghutchis 7111d 10h /tv80/trunk
59 Added lib for generating MPU interfaces ghutchis 7111d 10h /tv80/trunk
58 Made TX path async
Made TX clock input instead of output		 ghutchis 7150d 21h /tv80/trunk
57 Optimized read-back of data using INIR instruction ghutchis 7151d 04h /tv80/trunk
56 Updated env for simple_gmii with async clk ghutchis 7151d 04h /tv80/trunk
55 Added documentation of core area and the simple GMII interface block. ghutchis 7151d 06h /tv80/trunk
54 Test program for network interface ghutchis 7153d 03h /tv80/trunk
53 Added environment hooks for using and testing the GMII interface ghutchis 7153d 03h /tv80/trunk
52 Added simple GMII-like interface for testing ghutchis 7153d 03h /tv80/trunk
45 Added negedge version of top ghutchis 7168d 07h /tv80/trunk
44 Updated run script for better dump control ghutchis 7168d 09h /tv80/trunk
43 Fixed assembly routines for blk mem copy test ghutchis 7190d 22h /tv80/trunk
42 Added decode of OUT (##),A instruction
Removed dump-by-default and added DUMP_START define		 ghutchis 7190d 22h /tv80/trunk
41 Added random-read value port ghutchis 7193d 02h /tv80/trunk
40 Added random-read port and block memory instruction test ghutchis 7193d 02h /tv80/trunk
39 Added checksum port definitions, and test for block-OUT instructions ghutchis 7193d 04h /tv80/trunk
38 Added command-line options for help (-h) and run with instruction decode (-d) ghutchis 7194d 20h /tv80/trunk
37 Added new I/O registers for testing block I/O ghutchis 7194d 20h /tv80/trunk
36 Removed default instruction decode ghutchis 7194d 20h /tv80/trunk
35 Updated IO registers to add checksum and increment-on-read registers
used for testing block I/O instructions.		 ghutchis 7195d 07h /tv80/trunk
34 Created test for block I/O instructions ghutchis 7195d 07h /tv80/trunk
33 Added missing IncDec controls to OUTI/OUTD instructions ghutchis 7196d 04h /tv80/trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.