OpenCores
URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] [tv80/] [trunk] - Rev 98

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
98 Changed malloc for strings with constant length copy, add assertion checks for
null pointers in env memory, and fixed some formatting
ghutchis 5307d 19h /tv80/trunk
97 Added data in mux, added 16450 UART to environment ghutchis 5311d 23h /tv80/trunk
96 Added Z80 op decode to environment, enabled by -k switch ghutchis 5312d 04h /tv80/trunk
95 Updated regression script to use SystemC simulation ghutchis 5314d 00h /tv80/trunk
94 Ported over env_io.v from Verilog environment to tv_responder.
Basic tests from Verilog environment (hello, fib) now passing in
SystemC environment.
ghutchis 5316d 00h /tv80/trunk
93 Added common header file for all systemc environment ghutchis 5316d 23h /tv80/trunk
92 Added responder to top level, beginning of support for ihex load ghutchis 5321d 00h /tv80/trunk
91 Preliminary support for SystemC/Verilator environment ghutchis 5321d 03h /tv80/trunk
90 Fixed syntax errors in core preventing Verilator from compiling.
Added new capability to register generator to make registers which
latch on an external event. Removed spurious copyright notice.
ghutchis 5321d 03h /tv80/trunk
89 RTL and environment fixes for nmi bug ghutchis 5341d 06h /tv80/trunk
88 Fixed bug introduced by conversion of mcycle to one-hot FSM ghutchis 5342d 20h /tv80/trunk
87 Added additional ifdef signals to remove unneede R (refresh) register ghutchis 5358d 04h /tv80/trunk
84 New directory structure. root 5581d 16h /tv80/trunk
83 Some fixes from Guy-- replace case with casex. hharte 5654d 22h /trunk
82 Clean up spacing hharte 5664d 18h /trunk
81 Initial version of TV80 Wishbone Wrapper hharte 5664d 18h /trunk
80 Misc. code clean-up on mcode to make code smaller and (hopefully)
more readable.
ghutchis 6764d 07h /trunk
79 Added JR self-checking test ghutchis 6764d 07h /trunk
78 Hajime Ishitani pointed out missing invert on cs_n signal ghutchis 6807d 08h /trunk
77 Added back files lost after server crash ghutchis 6839d 02h /trunk
75 Modified environment I/O so multicycle wr_n signals are only seen as
a single write.
ghutchis 6918d 08h /trunk
74 Changed default for T2Write to be 1, to match expected behavior for
most users.
ghutchis 6918d 09h /trunk
73 Added RC4 encrypt/decrypt test ghutchis 6930d 04h /trunk
72 Added copyright header ghutchis 6930d 04h /trunk
71 Ported UART from T80 ghutchis 6991d 08h /trunk
70 Added test for T16450 UART ghutchis 7042d 03h /trunk
69 Added UART instance in testbench, and added UART to compile list. ghutchis 7042d 03h /trunk
68 Updated nwtest to reflect changes in register interface to simple_gmii.
In particular, interrupt bits for packet arrival and sending now need
to be explicitly cleared afterwards.
ghutchis 7050d 03h /trunk
67 Updated register generator based on testing with simple_gmii. Changed
how interrupt output mux is created, fixed many bugs.
ghutchis 7050d 03h /trunk
66 Modified top level testbench to reflect changes in simple_gmii block ghutchis 7050d 03h /trunk

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.