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[/] [uart16750/] [trunk] - Rev 25

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Rev Log message Author Age Path
25 UART16750: Updated testbench hasw 5054d 18h /uart16750/trunk
24 Inverted low active outputs when RST is active hasw 5054d 18h /uart16750/trunk
23 Fixed paths in Makefile for simulation hasw 5418d 21h /uart16750/trunk
22 Removed old stimuli data file, created by perl script hasw 5418d 21h /uart16750/trunk
21 Updated simulation files hasw 5418d 21h /uart16750/trunk
20 UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state hasw 5548d 19h /uart16750/trunk
17 New directory structure. root 5565d 05h /uart16750/trunk
16 UART16750: Added example project hasw 5585d 16h /trunk
15 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5594d 19h /trunk
14 UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests. hasw 5595d 21h /trunk
13 UART16750: Added automatic flow control hasw 5608d 21h /trunk
12 UART16750: Updated stimuli script with automatic flow control tests hasw 5608d 22h /trunk
11 UART16750: Removed dependency from std_logic_unsigned hasw 5608d 22h /trunk
10 UART16750: Removed dependency from std_logic_unsigned hasw 5608d 22h /trunk
9 Registered control line outputs hasw 5618d 00h /trunk
8 Make memory read in generic FIFO model synchronous for optimized used with XST hasw 5618d 00h /trunk
7 Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST hasw 5619d 04h /trunk
6 THR empty interrupt register connected to RST hasw 5619d 05h /trunk
5 Removed old component hasw 5619d 23h /trunk
4 Removed swap file hasw 5620d 00h /trunk
2 Imported sources hasw 5620d 00h /trunk
1 Standard project directories initialized by cvs2svn. 5620d 00h /trunk

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