OpenCores
URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] [v586/] - Rev 121

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Rev Log message Author Age Path
121 major update to support several board ultro 2831d 21h /v586
120 cleanup ultro 2831d 21h /v586
119 cleanup ultro 2831d 21h /v586
118 cleanup ultro 2831d 21h /v586
117 reset polarity in mig_b.prj for ddr2 was wrong , should be high ultro 2879d 01h /v586
116 fix path of the axi rom module ultro 2892d 20h /v586
115 update for synth slack ultro 2893d 14h /v586
114 update cosmetic ultro 2893d 15h /v586
113 updates to take acu appart ultro 2893d 16h /v586
112 Added the prj missing files ultro 2897d 04h /v586
111 added comment ultro 2913d 14h /v586
110 updated MCS files to be downloaded to nexys4 DDR ultro 2913d 14h /v586
109 update for nexys 4 ddr ultro 2913d 15h /v586
108 update xdc for nexys 4 ddr ultro 2913d 15h /v586
107 crossbar update ultro 2913d 15h /v586
106 update core netlist ultro 2913d 15h /v586
105 migration nexys ddr ultro 2913d 16h /v586
104 iadd rstgen and clk wiard for ddr nexys4 TOP ultro 2920d 16h /v586
103 commit top for 128mbyte nexys4 ddr version ultro 2930d 06h /v586
102 committed 128mbytes boot code for nexys4 ddr ultro 2930d 06h /v586
101 add ddr interface mig7 xilinx xci ip ultro 2930d 19h /v586
100 add crossbar for nexys4 ddr with 128megabyte ram window ultro 2930d 19h /v586
99 remove phy_intn from xdc constraints as it is not used inside design wi th etherlite. ultro 2972d 04h /v586
98 update tbench and add mii to rmii converter ip from xilinx ultro 2972d 14h /v586
97 update periph and TOP ultro 2972d 14h /v586
96 update periph , uart is not inside ultro 2972d 14h /v586
95 update boot.mem accordingly to test.s cleanup ultro 2974d 17h /v586
94 clean up test.s ultro 2974d 17h /v586
93 added stub for keyboard ultro 2975d 06h /v586
92 added doc ultro 2975d 07h /v586

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