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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 38

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Rev Log message Author Age Path
38 updated andor mux unneback 4876d 20h /versatile_library/trunk/rtl/verilog
37 corrected polynom with length 20 unneback 4882d 16h /versatile_library/trunk/rtl/verilog
36 added generic andor_mux unneback 4884d 01h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4884d 12h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4884d 12h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4897d 14h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4905d 00h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4924d 19h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4924d 20h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4924d 20h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4925d 21h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4925d 21h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4925d 22h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4926d 12h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4927d 20h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4928d 10h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4928d 15h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4929d 12h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4930d 23h /versatile_library/trunk/rtl/verilog
17 unneback 4994d 12h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 5000d 20h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 5001d 01h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 5001d 02h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 5001d 22h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 5002d 13h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 5004d 12h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 5004d 12h /versatile_library/trunk/rtl/verilog
7 mem update unneback 5004d 13h /versatile_library/trunk/rtl/verilog
6 added library files unneback 5017d 14h /versatile_library/trunk/rtl/verilog
5 memories added unneback 5017d 14h /versatile_library/trunk/rtl/verilog

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