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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 40

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Rev Log message Author Age Path
40 new build environment with custom.v added as a result file unneback 4882d 13h /versatile_library/trunk/rtl/verilog
39 added simple port prio based wb arbiter unneback 4883d 10h /versatile_library/trunk/rtl/verilog
38 updated andor mux unneback 4883d 10h /versatile_library/trunk/rtl/verilog
37 corrected polynom with length 20 unneback 4889d 06h /versatile_library/trunk/rtl/verilog
36 added generic andor_mux unneback 4890d 15h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4891d 02h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4891d 02h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4904d 04h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4911d 14h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4931d 09h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4931d 09h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4931d 10h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4932d 11h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4932d 11h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4932d 12h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4933d 02h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4934d 09h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4935d 00h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4935d 05h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4936d 01h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4937d 12h /versatile_library/trunk/rtl/verilog
17 unneback 5001d 02h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 5007d 10h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 5007d 15h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 5007d 16h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 5008d 12h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 5009d 03h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 5011d 02h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 5011d 02h /versatile_library/trunk/rtl/verilog
7 mem update unneback 5011d 03h /versatile_library/trunk/rtl/verilog

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