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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 40

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Rev Log message Author Age Path
40 new build environment with custom.v added as a result file unneback 4891d 19h /versatile_library/trunk/rtl/verilog
39 added simple port prio based wb arbiter unneback 4892d 16h /versatile_library/trunk/rtl/verilog
38 updated andor mux unneback 4892d 16h /versatile_library/trunk/rtl/verilog
37 corrected polynom with length 20 unneback 4898d 12h /versatile_library/trunk/rtl/verilog
36 added generic andor_mux unneback 4899d 21h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4900d 08h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4900d 08h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4913d 10h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4920d 20h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4940d 15h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4940d 16h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4940d 16h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4941d 17h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4941d 17h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4941d 18h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4942d 08h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4943d 16h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4944d 06h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4944d 12h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4945d 08h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4946d 19h /versatile_library/trunk/rtl/verilog
17 unneback 5010d 08h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 5016d 16h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 5016d 21h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 5016d 23h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 5017d 19h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 5018d 09h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 5020d 08h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 5020d 08h /versatile_library/trunk/rtl/verilog
7 mem update unneback 5020d 09h /versatile_library/trunk/rtl/verilog

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