OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog] - Rev 28

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4938d 14h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4938d 14h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4938d 15h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4939d 05h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4940d 13h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4941d 03h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4941d 08h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4942d 05h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4943d 16h /versatile_library/trunk/rtl/verilog
17 unneback 5007d 05h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 5013d 13h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 5013d 18h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 5013d 19h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 5014d 15h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 5015d 06h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 5017d 05h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 5017d 05h /versatile_library/trunk/rtl/verilog
7 mem update unneback 5017d 06h /versatile_library/trunk/rtl/verilog
6 added library files unneback 5030d 07h /versatile_library/trunk/rtl/verilog
5 memories added unneback 5030d 07h /versatile_library/trunk/rtl/verilog
4 added counters unneback 5034d 11h /versatile_library/trunk/rtl/verilog
3 various updates
counter added		 unneback 5037d 06h /versatile_library/trunk/rtl/verilog
2 initial check-in unneback 5038d 06h /versatile_library/trunk/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.