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[/] [versatile_library/] [trunk/] [rtl/] [verilog] - Rev 36

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Rev Log message Author Age Path
36 added generic andor_mux unneback 4876d 04h /versatile_library/trunk/rtl/verilog
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4876d 15h /versatile_library/trunk/rtl/verilog
34 added vl_mux2_andor and vl_mux3_andor unneback 4876d 15h /versatile_library/trunk/rtl/verilog
33 updated wb3wb3_bridge unneback 4889d 17h /versatile_library/trunk/rtl/verilog
32 added vl_pll for ALTERA (cycloneIII) unneback 4897d 03h /versatile_library/trunk/rtl/verilog
31 sync FIFO updated unneback 4916d 23h /versatile_library/trunk/rtl/verilog
30 updated counter for level1 and level2 function unneback 4916d 23h /versatile_library/trunk/rtl/verilog
29 updated counter for level1 and level2 function unneback 4916d 23h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4918d 00h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4918d 00h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4918d 02h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4918d 15h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4919d 23h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4920d 14h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4920d 19h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4921d 15h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4923d 02h /versatile_library/trunk/rtl/verilog
17 unneback 4986d 15h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 4992d 23h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 4993d 04h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 4993d 06h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 4994d 02h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 4994d 17h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 4996d 16h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 4996d 16h /versatile_library/trunk/rtl/verilog
7 mem update unneback 4996d 17h /versatile_library/trunk/rtl/verilog
6 added library files unneback 5009d 17h /versatile_library/trunk/rtl/verilog
5 memories added unneback 5009d 17h /versatile_library/trunk/rtl/verilog
4 added counters unneback 5013d 21h /versatile_library/trunk/rtl/verilog
3 various updates
counter added		 unneback 5016d 16h /versatile_library/trunk/rtl/verilog

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