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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk] - Rev 31

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31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 16h /versatile_mem_ctrl/trunk
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 16h /versatile_mem_ctrl/trunk
29 Adapted the test bench to the new wishbone interface. mikaeljf 5240d 16h /versatile_mem_ctrl/trunk
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5240d 18h /versatile_mem_ctrl/trunk
27 unneback 5244d 09h /versatile_mem_ctrl/trunk
26 compiles OK, not simulated unneback 5246d 08h /versatile_mem_ctrl/trunk
25 unneback 5246d 11h /versatile_mem_ctrl/trunk
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5246d 22h /versatile_mem_ctrl/trunk
23 Removed redundant code. mikaeljf 5254d 15h /versatile_mem_ctrl/trunk
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5256d 11h /versatile_mem_ctrl/trunk
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5260d 14h /versatile_mem_ctrl/trunk
20 Minor update of sdc-file. mikaeljf 5262d 15h /versatile_mem_ctrl/trunk
19 Added do-file for Modelsim waveform viewer. mikaeljf 5268d 20h /versatile_mem_ctrl/trunk
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5269d 17h /versatile_mem_ctrl/trunk
17 Modified rtl Makefile and tb_defines.v mikaeljf 5272d 16h /versatile_mem_ctrl/trunk
16 Added fizzim.pl mikaeljf 5272d 16h /versatile_mem_ctrl/trunk
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5273d 17h /versatile_mem_ctrl/trunk
14 Added external feedback of DDR SDRAM clock. mikaeljf 5363d 19h /versatile_mem_ctrl/trunk
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5363d 22h /versatile_mem_ctrl/trunk
12 Minor update of whishbone FSMs in TB mikaeljf 5373d 22h /versatile_mem_ctrl/trunk
11 Initial version with support for DDR mikaeljf 5374d 10h /versatile_mem_ctrl/trunk
10 unneback 5401d 18h /versatile_mem_ctrl/trunk
9 testbench unneback 5401d 18h /versatile_mem_ctrl/trunk
8 unneback 5497d 14h /versatile_mem_ctrl/trunk
7 unneback 5497d 15h /versatile_mem_ctrl/trunk
6 unneback 5497d 15h /versatile_mem_ctrl/trunk
5 pass initial testing unneback 5497d 15h /versatile_mem_ctrl/trunk
4 unneback 5498d 18h /versatile_mem_ctrl/trunk
3 unneback 5498d 21h /versatile_mem_ctrl/trunk
2 initial unneback 5504d 19h /versatile_mem_ctrl/trunk

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