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[/] [versatile_mem_ctrl/] [trunk] - Rev 49

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Rev Log message Author Age Path
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5253d 05h /versatile_mem_ctrl/trunk
48 dq_oe fix unneback 5253d 05h /versatile_mem_ctrl/trunk
47 support for registered outputs on ras, cas and we unneback 5253d 06h /versatile_mem_ctrl/trunk
46 cosmetic updates unneback 5253d 07h /versatile_mem_ctrl/trunk
45 added unneback 5253d 09h /versatile_mem_ctrl/trunk
44 registered row comparison unneback 5255d 09h /versatile_mem_ctrl/trunk
43 unneback 5255d 15h /versatile_mem_ctrl/trunk
42 added pipeline stage for egress FIFO readot unneback 5255d 22h /versatile_mem_ctrl/trunk
41 Added two alternate data capture functions. mikaeljf 5256d 06h /versatile_mem_ctrl/trunk
40 updated fifo interfaces with re/rd and we/wr unneback 5256d 13h /versatile_mem_ctrl/trunk
39 updated FIFO and SDR 16 unneback 5257d 01h /versatile_mem_ctrl/trunk
38 casex in rw state to save logic unneback 5259d 08h /versatile_mem_ctrl/trunk
37 unneback 5259d 23h /versatile_mem_ctrl/trunk
36 unneback 5259d 23h /versatile_mem_ctrl/trunk
35 work for limited test case unneback 5260d 06h /versatile_mem_ctrl/trunk
34 added unneback 5260d 07h /versatile_mem_ctrl/trunk
33 work for limited test case, no cke inhibit for fifo empty unneback 5260d 09h /versatile_mem_ctrl/trunk
32 Updated the testbench to match the new wishbone interface. mikaeljf 5263d 13h /versatile_mem_ctrl/trunk
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5265d 06h /versatile_mem_ctrl/trunk
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5265d 06h /versatile_mem_ctrl/trunk
29 Adapted the test bench to the new wishbone interface. mikaeljf 5269d 06h /versatile_mem_ctrl/trunk
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5269d 08h /versatile_mem_ctrl/trunk
27 unneback 5272d 23h /versatile_mem_ctrl/trunk
26 compiles OK, not simulated unneback 5274d 23h /versatile_mem_ctrl/trunk
25 unneback 5275d 01h /versatile_mem_ctrl/trunk
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5275d 12h /versatile_mem_ctrl/trunk
23 Removed redundant code. mikaeljf 5283d 05h /versatile_mem_ctrl/trunk
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5285d 01h /versatile_mem_ctrl/trunk
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5289d 04h /versatile_mem_ctrl/trunk
20 Minor update of sdc-file. mikaeljf 5291d 06h /versatile_mem_ctrl/trunk

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