Rev |
Log message |
Author |
Age |
Path |
50 |
Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily |
julius |
5224d 08h |
/versatile_mem_ctrl/trunk |
49 |
Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project |
julius |
5224d 10h |
/versatile_mem_ctrl/trunk |
48 |
dq_oe fix |
unneback |
5224d 10h |
/versatile_mem_ctrl/trunk |
47 |
support for registered outputs on ras, cas and we |
unneback |
5224d 10h |
/versatile_mem_ctrl/trunk |
46 |
cosmetic updates |
unneback |
5224d 11h |
/versatile_mem_ctrl/trunk |
45 |
added |
unneback |
5224d 14h |
/versatile_mem_ctrl/trunk |
44 |
registered row comparison |
unneback |
5226d 14h |
/versatile_mem_ctrl/trunk |
43 |
|
unneback |
5226d 19h |
/versatile_mem_ctrl/trunk |
42 |
added pipeline stage for egress FIFO readot |
unneback |
5227d 03h |
/versatile_mem_ctrl/trunk |
41 |
Added two alternate data capture functions. |
mikaeljf |
5227d 11h |
/versatile_mem_ctrl/trunk |
40 |
updated fifo interfaces with re/rd and we/wr |
unneback |
5227d 18h |
/versatile_mem_ctrl/trunk |
39 |
updated FIFO and SDR 16 |
unneback |
5228d 05h |
/versatile_mem_ctrl/trunk |
38 |
casex in rw state to save logic |
unneback |
5230d 13h |
/versatile_mem_ctrl/trunk |
37 |
|
unneback |
5231d 03h |
/versatile_mem_ctrl/trunk |
36 |
|
unneback |
5231d 04h |
/versatile_mem_ctrl/trunk |
35 |
work for limited test case |
unneback |
5231d 11h |
/versatile_mem_ctrl/trunk |
34 |
added |
unneback |
5231d 11h |
/versatile_mem_ctrl/trunk |
33 |
work for limited test case, no cke inhibit for fifo empty |
unneback |
5231d 13h |
/versatile_mem_ctrl/trunk |
32 |
Updated the testbench to match the new wishbone interface. |
mikaeljf |
5234d 17h |
/versatile_mem_ctrl/trunk |
31 |
Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. |
mikaeljf |
5236d 10h |
/versatile_mem_ctrl/trunk |
30 |
Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. |
mikaeljf |
5236d 10h |
/versatile_mem_ctrl/trunk |
29 |
Adapted the test bench to the new wishbone interface. |
mikaeljf |
5240d 11h |
/versatile_mem_ctrl/trunk |
28 |
Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. |
mikaeljf |
5240d 12h |
/versatile_mem_ctrl/trunk |
27 |
|
unneback |
5244d 04h |
/versatile_mem_ctrl/trunk |
26 |
compiles OK, not simulated |
unneback |
5246d 03h |
/versatile_mem_ctrl/trunk |
25 |
|
unneback |
5246d 06h |
/versatile_mem_ctrl/trunk |
24 |
Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. |
mikaeljf |
5246d 17h |
/versatile_mem_ctrl/trunk |
23 |
Removed redundant code. |
mikaeljf |
5254d 10h |
/versatile_mem_ctrl/trunk |
22 |
Updated the Altera timing constraints file, also minor updates of defines file and Makefile. |
mikaeljf |
5256d 06h |
/versatile_mem_ctrl/trunk |
21 |
Updated the Altera timing constraints file (.sdc). |
mikaeljf |
5260d 09h |
/versatile_mem_ctrl/trunk |