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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 42

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Rev Log message Author Age Path
42 added pipeline stage for egress FIFO readot unneback 5227d 07h /versatile_mem_ctrl
41 Added two alternate data capture functions. mikaeljf 5227d 15h /versatile_mem_ctrl
40 updated fifo interfaces with re/rd and we/wr unneback 5227d 22h /versatile_mem_ctrl
39 updated FIFO and SDR 16 unneback 5228d 09h /versatile_mem_ctrl
38 casex in rw state to save logic unneback 5230d 17h /versatile_mem_ctrl
37 unneback 5231d 07h /versatile_mem_ctrl
36 unneback 5231d 08h /versatile_mem_ctrl
35 work for limited test case unneback 5231d 15h /versatile_mem_ctrl
34 added unneback 5231d 16h /versatile_mem_ctrl
33 work for limited test case, no cke inhibit for fifo empty unneback 5231d 18h /versatile_mem_ctrl
32 Updated the testbench to match the new wishbone interface. mikaeljf 5234d 22h /versatile_mem_ctrl
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 15h /versatile_mem_ctrl
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 15h /versatile_mem_ctrl
29 Adapted the test bench to the new wishbone interface. mikaeljf 5240d 15h /versatile_mem_ctrl
28 Fixed typos and updated the rtl Makefile and Altera-Modelsim script. Modified the counter-excel file and added missing module 'dff_sr.v'. mikaeljf 5240d 17h /versatile_mem_ctrl
27 unneback 5244d 08h /versatile_mem_ctrl
26 compiles OK, not simulated unneback 5246d 07h /versatile_mem_ctrl
25 unneback 5246d 10h /versatile_mem_ctrl
24 Updated the memory controller according to recent update of Versatile_counter. Modified the rtl Makefile and added an excel file with counter definitions. mikaeljf 5246d 21h /versatile_mem_ctrl
23 Removed redundant code. mikaeljf 5254d 14h /versatile_mem_ctrl
22 Updated the Altera timing constraints file, also minor updates of defines file and Makefile. mikaeljf 5256d 10h /versatile_mem_ctrl
21 Updated the Altera timing constraints file (.sdc). mikaeljf 5260d 13h /versatile_mem_ctrl
20 Minor update of sdc-file. mikaeljf 5262d 15h /versatile_mem_ctrl
19 Added do-file for Modelsim waveform viewer. mikaeljf 5268d 19h /versatile_mem_ctrl
18 Updated the rtl/verilog Makefile and the bench Makefile. mikaeljf 5269d 16h /versatile_mem_ctrl
17 Modified rtl Makefile and tb_defines.v mikaeljf 5272d 15h /versatile_mem_ctrl
16 Added fizzim.pl mikaeljf 5272d 16h /versatile_mem_ctrl
15 Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera. mikaeljf 5273d 16h /versatile_mem_ctrl
14 Added external feedback of DDR SDRAM clock. mikaeljf 5363d 18h /versatile_mem_ctrl
13 Modified DDR FSM for read and write, added counters for burst length, read/write latency, write recovery time etc. Added DCM with external feedback. mikaeljf 5363d 21h /versatile_mem_ctrl

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