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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl] - Rev 59

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Rev Log message Author Age Path
59 counter changed to shift register unneback 5217d 16h /versatile_mem_ctrl
58 sdr_16 fixes for timing - extra egress register stage, appropriate changes in sdr_16 fsm julius 5218d 17h /versatile_mem_ctrl
57 added support for early termination of burst access unneback 5219d 19h /versatile_mem_ctrl
56 corrected fifo_rd_data in state w4d unneback 5221d 12h /versatile_mem_ctrl
55 Fixed up sdr16 dqm output julius 5222d 07h /versatile_mem_ctrl
54 dqm moved into FSM unneback 5223d 04h /versatile_mem_ctrl
53 unneback 5223d 04h /versatile_mem_ctrl
52 act exit for read updated unneback 5224d 06h /versatile_mem_ctrl
51 act exit for read updated unneback 5224d 06h /versatile_mem_ctrl
50 Fixed up make file - THIS MAY BREAK THINGS, but it's a lot neater and easier to use, also dependencies are now properly configured, and we don't remake things unecessarily julius 5224d 08h /versatile_mem_ctrl
49 Added versatile_fifo_dual_port_ram_dc_sw.v rule to makefile, getting it from versatile fifo project julius 5224d 10h /versatile_mem_ctrl
48 dq_oe fix unneback 5224d 10h /versatile_mem_ctrl
47 support for registered outputs on ras, cas and we unneback 5224d 10h /versatile_mem_ctrl
46 cosmetic updates unneback 5224d 11h /versatile_mem_ctrl
45 added unneback 5224d 14h /versatile_mem_ctrl
44 registered row comparison unneback 5226d 13h /versatile_mem_ctrl
43 unneback 5226d 19h /versatile_mem_ctrl
42 added pipeline stage for egress FIFO readot unneback 5227d 03h /versatile_mem_ctrl
41 Added two alternate data capture functions. mikaeljf 5227d 10h /versatile_mem_ctrl
40 updated fifo interfaces with re/rd and we/wr unneback 5227d 17h /versatile_mem_ctrl
39 updated FIFO and SDR 16 unneback 5228d 05h /versatile_mem_ctrl
38 casex in rw state to save logic unneback 5230d 13h /versatile_mem_ctrl
37 unneback 5231d 03h /versatile_mem_ctrl
36 unneback 5231d 03h /versatile_mem_ctrl
35 work for limited test case unneback 5231d 11h /versatile_mem_ctrl
34 added unneback 5231d 11h /versatile_mem_ctrl
33 work for limited test case, no cke inhibit for fifo empty unneback 5231d 13h /versatile_mem_ctrl
32 Updated the testbench to match the new wishbone interface. mikaeljf 5234d 17h /versatile_mem_ctrl
31 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 10h /versatile_mem_ctrl
30 Added Xilinx primitive for dff_sr.v module, updated rtl-Makefile adn simulation scripts. mikaeljf 5236d 10h /versatile_mem_ctrl

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