URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

Subversion Repositories virtex7_pcie_dma

[/] [virtex7_pcie_dma/] - Rev 29

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Rev	Log message	Author	Age	Path
29	Improved application to reflect both up and down transfers	fransschreuder	3124d 00h	/virtex7_pcie_dma
28	Added registermap reset	fransschreuder	3124d 02h	/virtex7_pcie_dma
27	Fixed: * BUG 2580: Missing packets in receive (PC => FPGA) path Changed: * Client tags now handled by Xilinx IP core * fifo signals to reflect upfifo and downfifo naming	fransschreuder	3124d 05h	/virtex7_pcie_dma
26	Added sys_clk constraint	fransschreuder	3124d 07h	/virtex7_pcie_dma
25	Added scripts and constraints for KCU105	fransschreuder	3124d 08h	/virtex7_pcie_dma
24	Added: * Support for KCU105 board in code TODO * Add constraints and build scripts for KCU105	fransschreuder	3125d 01h	/virtex7_pcie_dma
23	Fixed reset of application registers	fransschreuder	3182d 07h	/virtex7_pcie_dma
22	Added dma_soft_reset to trigger register resets	fransschreuder	3188d 06h	/virtex7_pcie_dma
21	Fixed BUG http://opencores.org/bug,view,2562	fransschreuder	3197d 04h	/virtex7_pcie_dma
20	Fixed: * Missing packets if the fifo goes empty during a TLP * Dynamically change the empty threshold of the main fifo to TLP size	fransschreuder	3211d 02h	/virtex7_pcie_dma
19	* driver/README updated	oussamak	3217d 04h	/virtex7_pcie_dma
18	Changed: * Added drivers * Added Wupper tools for debugging * Added card ID register	oussamak	3217d 06h	/virtex7_pcie_dma
17	Changed name of toplevel, to make tree consistent	oussamak	3231d 09h	/virtex7_pcie_dma
16	MODIFED: -- top level name to wupper_oc (including scripts)	aborga	3281d 02h	/virtex7_pcie_dma
15	MODIFIED: -- Renamed core to Wupper (vhdl files) -- Changed width of interrupt enable to number_of_interrupts	fransschreuder	3281d 03h	/virtex7_pcie_dma
14	RENAMED: -- simulation folder	aborga	3281d 04h	/virtex7_pcie_dma
13	RENAMED: -- script	aborga	3281d 04h	/virtex7_pcie_dma
12	Fixed http://opencores.org/bug,view,2524	fransschreuder	3356d 04h	/virtex7_pcie_dma
11	MODIFIED: -- updated documentation	aborga	3369d 02h	/virtex7_pcie_dma
10	Changed: LOC => Package_pin	fransschreuder	3379d 02h	/virtex7_pcie_dma
9	Added actual version information (Build date and svn revision) in BOARD_ID register	fransschreuder	3408d 00h	/virtex7_pcie_dma
8	Changed: * Added support for circular DMA (wrap around) * Fixed Read / Write interrupts	fransschreuder	3408d 07h	/virtex7_pcie_dma
7	Changed: * Simplified address calculation to relax timing * Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing * Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk * Added support for the High tech Global HTG710 board	fransschreuder	3448d 03h	/virtex7_pcie_dma
6	Changed: * fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable * Fixed missing signals in sensitivity list	fransschreuder	3454d 01h	/virtex7_pcie_dma
5	Changed: * Added two registers to test interrupts vectors 2 and 3 * Added a register to read generic constants to show number of interrupts / number of descriptors * fixed consistency of generic default values among different design units * fixed route of pll_locked / register map record, to allow non-flattening of synthesis	fransschreuder	3455d 05h	/virtex7_pcie_dma
4	fixed a typo in the interrupt table documentation	fransschreuder	3467d 01h	/virtex7_pcie_dma
3	Created: First commit of the full PCIe DMA Core Including: -Firmware -Vivado .tcl scripts -Questasim simulation scripts -Documentation (Latex / Doxygen script)	fransschreuder	3467d 02h	/virtex7_pcie_dma
2	Added firmware directory	fransschreuder	3470d 00h	/virtex7_pcie_dma
1	The project and the structure was created	root	3488d 19h	/virtex7_pcie_dma

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[/] [virtex7_pcie_dma/] - Rev 29

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