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[/] [xgate/] [trunk/] [bench] - Rev 95

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Rev Log message Author Age Path
95 Covers all 127 interrupts with one service routine. rehayes 4626d 03h /xgate/trunk/bench
94 Update irq test to check all interrupts, add sync reset test. All this to improve code coverage. rehayes 4626d 03h /xgate/trunk/bench
93 Initial revision, memory image for skipjack test. rehayes 4626d 03h /xgate/trunk/bench
89 Code cleanup. rehayes 4640d 02h /xgate/trunk/bench
86 Add JTAG test tasks rehayes 4840d 01h /xgate/trunk/bench
82 Added debug module to assist in software debugging. rehayes 5115d 05h /xgate/trunk/bench
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5205d 09h /xgate/trunk/bench
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5206d 12h /xgate/trunk/bench
65 Parameterize delays based on number of RAM wait states. rehayes 5226d 08h /xgate/trunk/bench
62 Cleanup implicit wire declarations. rehayes 5236d 07h /xgate/trunk/bench
60 Add ability at insert wait states on RAM access rehayes 5243d 07h /xgate/trunk/bench
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5311d 11h /xgate/trunk/bench
50 incremental update to match status bit changes rehayes 5327d 07h /xgate/trunk/bench
41 Update for singel program counter added, WISHBONE Slave bus word addressability and byte selection rehayes 5362d 07h /xgate/trunk/bench
39 delete rehayes 5390d 11h /xgate/trunk/bench
37 RAM model breakout for testbench rehayes 5390d 12h /xgate/trunk/bench
36 Added bus arbitration for slave bus, but not fully functional yet. Added byte lane selects to task calls. rehayes 5390d 12h /xgate/trunk/bench
35 Add byte lane select input to all tasks rehayes 5390d 12h /xgate/trunk/bench
27 Subversion test, no actual code changes rehayes 5415d 06h /xgate/trunk/bench
21 Added timeout, total error count, and XGCHN test rehayes 5423d 07h /xgate/trunk/bench
20 Added event signal for compare error tracking in top level test bench. rehayes 5423d 07h /xgate/trunk/bench
19 Verilog memory image for testing rehayes 5423d 07h /xgate/trunk/bench
18 Complete XGCHN test code rehayes 5423d 07h /xgate/trunk/bench
13 Debug functions test code rehayes 5437d 07h /xgate/trunk/bench
11 Update with Single Step debuging test rehayes 5437d 07h /xgate/trunk/bench
10 Minor Cleanup rehayes 5442d 07h /xgate/trunk/bench
9 Update for new testbench usage rehayes 5443d 06h /xgate/trunk/bench
8 Clean up, Fix default ISR rehayes 5443d 06h /xgate/trunk/bench
7 Fix to take advantage of change to sconv program. rehayes 5449d 05h /xgate/trunk/bench
6 Update to create output file name from input file name by changing extension to .v rehayes 5449d 05h /xgate/trunk/bench

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