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[/] [xgate/] [trunk] - Rev 81

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Rev Log message Author Age Path
81 Initial checkin of the SKIPJACK encrypt/decrypt application program rehayes 5087d 12h /xgate/trunk
80 Added IRQ bypass registers and Test bench appendix rehayes 5149d 13h /xgate/trunk
79 Added IRQ bypass registers and Test bench appendix rehayes 5149d 13h /xgate/trunk
78 Added IRQ bypass registers and Test bench appendix rehayes 5149d 13h /xgate/trunk
77 Documentation update rehayes 5149d 13h /xgate/trunk
76 Updated xgate_risc.v for xlink synthesis warnings. rehayes 5172d 14h /xgate/trunk
75 Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 rehayes 5172d 14h /xgate/trunk
74 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5177d 15h /xgate/trunk
73 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5177d 15h /xgate/trunk
72 Code cleanup, eliminated index 0 of input and output interrupts. rehayes 5177d 15h /xgate/trunk
71 Added irq bypass registers to rtl, testbench and doc. rehayes 5178d 18h /xgate/trunk
70 Updated with interrupt bypass controll registers. rehayes 5178d 18h /xgate/trunk
69 New test to verify irq interrupt priority encoder. rehayes 5178d 18h /xgate/trunk
68 Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. rehayes 5178d 18h /xgate/trunk
67 Added irq bypass function and controll registers. Made lowest interrupt index highest priority. rehayes 5178d 18h /xgate/trunk
66 Fix testbench and RISC core related to debug mode and wait states. rehayes 5198d 14h /xgate/trunk
65 Parameterize delays based on number of RAM wait states. rehayes 5198d 14h /xgate/trunk
64 Fixed more bugs related to wait states and debug mode. rehayes 5198d 14h /xgate/trunk
63 Remove historical output ports that are no longer used. rehayes 5208d 14h /xgate/trunk
62 Cleanup implicit wire declarations. rehayes 5208d 14h /xgate/trunk
61 Update to RISC block to fix DEBUG mode, testbench update rehayes 5215d 13h /xgate/trunk
60 Add ability at insert wait states on RAM access rehayes 5215d 14h /xgate/trunk
59 Fix bug in entering DEBUG mode from WB bus command rehayes 5215d 14h /xgate/trunk
58 WISHBONE Bus update. rehayes 5267d 13h /xgate/trunk
57 Traded 16 data registers for 5 address regester when wait states are enabled. rehayes 5267d 16h /xgate/trunk
56 Extensive changes to testbench and the Xgate master bus interface and the way the RISC handles wait states. rehayes 5283d 17h /xgate/trunk
55 Minor change to instruction set details. rehayes 5283d 17h /xgate/trunk
54 complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module. rehayes 5283d 17h /xgate/trunk
53 Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal. rehayes 5283d 17h /xgate/trunk
52 Minor changes to aide waveform debug rehayes 5283d 17h /xgate/trunk

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