Rev |
Log message |
Author |
Age |
Path |
89 |
Code cleanup. |
rehayes |
4612d 06h |
/xgate |
88 |
Updated with complete code |
rehayes |
4685d 15h |
/xgate |
87 |
First pass JTAG TAP, state machine working but needs work to complete reset of TAP. |
rehayes |
4812d 05h |
/xgate |
86 |
Add JTAG test tasks |
rehayes |
4812d 05h |
/xgate |
85 |
Corrections to instruction set details example code, added test bench debugger. |
rehayes |
5086d 14h |
/xgate |
84 |
Added notes on SKIPJACK encrypt/decrypt applications, testbench debugger and user guide corrections. |
rehayes |
5086d 15h |
/xgate |
83 |
Add subroutine quailifier. |
rehayes |
5086d 15h |
/xgate |
82 |
Added debug module to assist in software debugging. |
rehayes |
5087d 09h |
/xgate |
81 |
Initial checkin of the SKIPJACK encrypt/decrypt application program |
rehayes |
5087d 10h |
/xgate |
80 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5149d 10h |
/xgate |
79 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5149d 10h |
/xgate |
78 |
Added IRQ bypass registers and Test bench appendix |
rehayes |
5149d 10h |
/xgate |
77 |
Documentation update |
rehayes |
5149d 10h |
/xgate |
76 |
Updated xgate_risc.v for xlink synthesis warnings. |
rehayes |
5172d 11h |
/xgate |
75 |
Fixed xlink synthesis warnings noted by Nachiket Jugade, missing else statment for chid_sm_ns line 393, mising default on shifter lines 2382 |
rehayes |
5172d 12h |
/xgate |
74 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5177d 13h |
/xgate |
73 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5177d 13h |
/xgate |
72 |
Code cleanup, eliminated index 0 of input and output interrupts. |
rehayes |
5177d 13h |
/xgate |
71 |
Added irq bypass registers to rtl, testbench and doc. |
rehayes |
5178d 15h |
/xgate |
70 |
Updated with interrupt bypass controll registers. |
rehayes |
5178d 15h |
/xgate |
69 |
New test to verify irq interrupt priority encoder. |
rehayes |
5178d 16h |
/xgate |
68 |
Added new test for interrupt priority and updated WISHBONE slave module with semaphore register. |
rehayes |
5178d 16h |
/xgate |
67 |
Added irq bypass function and controll registers. Made lowest interrupt index highest priority. |
rehayes |
5178d 16h |
/xgate |
66 |
Fix testbench and RISC core related to debug mode and wait states. |
rehayes |
5198d 12h |
/xgate |
65 |
Parameterize delays based on number of RAM wait states. |
rehayes |
5198d 12h |
/xgate |
64 |
Fixed more bugs related to wait states and debug mode. |
rehayes |
5198d 12h |
/xgate |
63 |
Remove historical output ports that are no longer used. |
rehayes |
5208d 12h |
/xgate |
62 |
Cleanup implicit wire declarations. |
rehayes |
5208d 12h |
/xgate |
61 |
Update to RISC block to fix DEBUG mode, testbench update |
rehayes |
5215d 11h |
/xgate |
60 |
Add ability at insert wait states on RAM access |
rehayes |
5215d 11h |
/xgate |