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[/] [xge_mac/] [trunk] - Rev 29

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Rev Log message Author Age Path
29 Adding parameter for max frame size antanguay 4245d 16h /xge_mac/trunk
28 Adding parameter for max frame size antanguay 4245d 17h /xge_mac/trunk
27 Fix octets stats on barrel shift transitions antanguay 4294d 16h /xge_mac/trunk
26 Fix packet count antanguay 4300d 16h /xge_mac/trunk
25 Timing improvements, reduced FIFO size from 1024 to 512 antanguay 4300d 18h /xge_mac/trunk
24 Use FIFO's for statistics clock domain crossing antanguay 4300d 19h /xge_mac/trunk
23 Adding basic packet stats antanguay 4301d 01h /xge_mac/trunk
22 Added prototype system verilog testbench antanguay 4302d 22h /xge_mac/trunk
21 Improvements for timing, adding alternate FIFO design using XIL define antanguay 4302d 22h /xge_mac/trunk
20 Updates for Xilinx synthesis antanguay 4592d 17h /xge_mac/trunk
19 Updates for 32/64 bit systems antanguay 4767d 18h /xge_mac/trunk
18 Updates for linux 32-bit antanguay 4768d 14h /xge_mac/trunk
17 Fixed deprecated SystemC warnings antanguay 4770d 22h /xge_mac/trunk
16 Rename tb_xge_mac.v to sv extension to fix issue with newer Modelsim antanguay 4771d 05h /xge_mac/trunk
15 Updated for Verilator 3.813 antanguay 4790d 05h /xge_mac/trunk
14 Change interface to big endian, added serdes examples to testbench antanguay 5378d 23h /xge_mac/trunk
13 Change interface to big endian, added serdes examples to testbench antanguay 5379d 00h /xge_mac/trunk
12 Change interface to big endian, added serdes examples to testbench antanguay 5379d 00h /xge_mac/trunk
11 Fixed clock crossing antanguay 5484d 22h /xge_mac/trunk
10 Added details to spec antanguay 5582d 17h /xge_mac/trunk
7 New directory structure. root 5657d 09h /xge_mac/trunk
6 Updated spec. Added mod[2:0] signals. Timing improvements. antanguay 5933d 17h /trunk
5 Fixed compilation antanguay 5939d 18h /trunk
4 Created antanguay 5939d 20h /trunk
2 Initial revision antanguay 5939d 21h /trunk
1 Standard project directories initialized by cvs2svn. 5939d 21h /trunk

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