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[/] [xucpu/] [trunk/] - Rev 33

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Rev Log message Author Age Path
33 Removal of simple compilation errors. lcdsgmtr 3072d 03h /xucpu/trunk
32 Added necessary red tape for implementing all these components. lcdsgmtr 3072d 03h /xucpu/trunk
31 Definition of system architecture library.
Definition of top level system architecture.
Main components used in top level system definition.		 lcdsgmtr 3072d 03h /xucpu/trunk
30 First implementation of cache memory. lcdsgmtr 3072d 03h /xucpu/trunk
29 All kinds of changes in different configurations. lcdsgmtr 3072d 03h /xucpu/trunk
28 Added project files for different systems. lcdsgmtr 3224d 04h /xucpu/trunk
27 When loading the 32k memory, do not let the process stop by a file that is
shorter, also make sure that the process is stopped if the file should be
longer.		 lcdsgmtr 3224d 04h /xucpu/trunk
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3226d 03h /xucpu/trunk
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3226d 03h /xucpu/trunk
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3226d 03h /xucpu/trunk
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3226d 03h /xucpu/trunk
22 Update on makefile, because some parts are in other files. lcdsgmtr 3226d 03h /xucpu/trunk
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3226d 03h /xucpu/trunk
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3226d 03h /xucpu/trunk
19 Makefile for building memory block testbench. lcdsgmtr 3226d 03h /xucpu/trunk
18 Ignore work files from GHDL. lcdsgmtr 3226d 03h /xucpu/trunk
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3226d 03h /xucpu/trunk
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3226d 03h /xucpu/trunk
15 Unification of all RAM parts into one interface. lcdsgmtr 3226d 03h /xucpu/trunk
14 Simple implementation project. lcdsgmtr 3358d 01h /xucpu/trunk
13 Updated smallest Xilinx configuration. lcdsgmtr 3358d 01h /xucpu/trunk
12 Update Xilinx configurations. lcdsgmtr 3358d 01h /xucpu/trunk
11 Successful run of the simulation. Correct results. lcdsgmtr 3358d 03h /xucpu/trunk
10 Correct build with GHDL. lcdsgmtr 3358d 03h /xucpu/trunk
9 This makes sure that this GHDL configuration analyses correctly. lcdsgmtr 3358d 03h /xucpu/trunk
8 Rebuilding the configuration to build the first system using GHDL. lcdsgmtr 3359d 02h /xucpu/trunk
7 Moved package for initialising memory also to src. lcdsgmtr 3359d 02h /xucpu/trunk
6 Removed some unnecessary files and directories.
Moved other files to new directories.		 lcdsgmtr 3359d 02h /xucpu/trunk
5 Re-organisation of repository. lcdsgmtr 3360d 03h /xucpu/trunk
4 Added directories for guiding implementation using Xilinx ISE and GHDL. lcdsgmtr 3395d 03h /xucpu/trunk

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