| Rev |
Log message |
Author |
Age |
Path |
| 118 |
Lots of changes. The biggest are to the CPU: MPYxHI instructions are now
verified to be working, ILLegal instructions stop at the right location,
the STEP bit no longer self-clears, etc. Other changes cleaned up the
internal documentation and removed parameters that should only have local
scope from the global parameter list. The NEW_INSTRUCTION_SET was also
removed from the CPU, since ... it's been new for too long to really be new
anymore. |
dgisselq |
2783d 18h |
/xulalx25soc |
| 117 |
Updates, to include new README and bench/cpp/Makefile that doesnt depend upon
a static VERILATOR_ROOT location. |
dgisselq |
2808d 10h |
/xulalx25soc |
| 116 |
Fixes a compiler warning about signed versus unsigned comparison, by forcing
the comparison to be signed. |
dgisselq |
2892d 20h |
/xulalx25soc |
| 115 |
Made the SDCard support dependent upon a XULA25 macro, which is defined at the
top of the file. Remove the XULA25 macro definition, and this will build
assuming a XULA9 configuration. |
dgisselq |
2901d 11h |
/xulalx25soc |
| 114 |
Added ZipBones to the list of dependencies, so this will (should) build
properly for the XULA9 as well as the XULA25. |
dgisselq |
2901d 11h |
/xulalx25soc |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2901d 11h |
/xulalx25soc |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
2903d 17h |
/xulalx25soc |
| 111 |
Added some debug support programs to the repository. |
dgisselq |
2909d 10h |
/xulalx25soc |
| 110 |
Fixed a problem whereby block RAM would be declared as a bus error on the
stack, even if the data was valid. |
dgisselq |
2909d 15h |
/xulalx25soc |
| 109 |
This continues the updates to the wishbone-uart conversion. It fixes several
bugs within wbuexec, and pipelines the compression scheme. Further, the
read codeword was adjusted so that a read of 8 can be requested with six-bits,
rather than requiring 12. Likewise, the dependence upon the read of 8 on
incrementing the address pointer has been removed. All told, the design
builds for a 200MHz Artix-7, and it has been tested with the CMod-S6. (Writing
flash seems to be one of the most comprehensive tests ...) |
dgisselq |
2909d 19h |
/xulalx25soc |
| 108 |
Minor documentation updates. |
dgisselq |
2910d 05h |
/xulalx25soc |
| 107 |
Minor change. |
dgisselq |
2910d 05h |
/xulalx25soc |
| 106 |
Minor, inconsequential changes. |
dgisselq |
2910d 05h |
/xulalx25soc |
| 105 |
Mostly cosmetic changes. The Makefile now builds a couple more programs,
the documentation is better, etc. |
dgisselq |
2910d 05h |
/xulalx25soc |
| 104 |
Updates to the flash driver drawn from the S6SoC project. |
dgisselq |
2910d 05h |
/xulalx25soc |
| 103 |
Added a SDSPI scope, and defined which of the four scopes it points to.
(It uses the configuration scopes position, if the configuration scope isn't
defined.) |
dgisselq |
2910d 06h |
/xulalx25soc |
| 102 |
Updated documentation. The documentation for these now also reflects that
these were drawn from an FPGA Library project, that is shared among many
FPGA builds. |
dgisselq |
2910d 06h |
/xulalx25soc |
| 101 |
Fixed the `defines at the top so that this can be built without any CPU.
This was then used to measure the impact of the CPU on the entire build, as
you could now build with no CPU, and then with a CPU to compare. |
dgisselq |
2910d 06h |
/xulalx25soc |
| 100 |
Includes updates so this can run at higher clocks speeds within an FPGA. |
dgisselq |
2910d 06h |
/xulalx25soc |
| 99 |
Includes high-speed updates. rxuart and txuart will now run at 200MHz on
an Artix-7, so should not impact timing (any more) on the XuLA platform. |
dgisselq |
2910d 06h |
/xulalx25soc |
| 98 |
Updated copyright notices for the new year, to reflect that changes have been
made in 2016. |
dgisselq |
2910d 06h |
/xulalx25soc |
| 97 |
Latest working bit file, with all changes attached as of this date. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 93 |
Oops -- missed adjusting the copyright. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 92 |
Fixes the problem whereby the master counters show when the user counters should
be showing and vice versa. Now the master counters show by default, together
with their correct labels. User counters are still available by pressing
'u' in the debugger, and the master counter display may be returned to by
pressing 'm' in the debugger. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 91 |
Fixes bugs associated with an overflow of write acknowledgements in the
receiver. This helps keep our accesses aligned. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 90 |
Reads and writes to the SD over SPI port now work. The card appears, as of now,
to be fully functional. |
dgisselq |
2933d 10h |
/xulalx25soc |
| 89 |
Bug fixes, following the adf_ce logic combining ALU/DIVIDE/FPU pipeline logic
into one register, this fixes that logic so that instructions without their
condition fulfilled are still "executed" and marked as done. |
dgisselq |
2933d 10h |
/xulalx25soc |
