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[/] - Rev 42

Rev	Log message	Author	Age	Path
42	This commit was manufactured by cvs2svn to create tag 'rel_12'.		7959d 04h	/
41	Changed synthesizeable FPGA memory implementation. Fixed some issues with Xilinx BlockRAM	rherveille	7959d 04h	/
40	Updated PDF.	lampret	8003d 07h	/
39	Added Richard's feedback.	lampret	8005d 07h	/
38	Undeleted	mohor	8025d 21h	/
37	no message	bbeaver	8262d 03h	/
36	minor changes: unified with all common rams	samg	8282d 12h	/
35	corrected output: output not valid if ce low	samg	8282d 17h	/
34	added valid checks to behvioral model	samg	8282d 17h	/
33	added checks and task in behavioral section	samg	8283d 18h	/
32	no message	bbeaver	8285d 00h	/
31	no message	bbeaver	8289d 00h	/
30	no message	bbeaver	8289d 23h	/
29	got timing checks mostly correct No functional stuff yet	bbeaver	8290d 00h	/
28	no message	bbeaver	8291d 00h	/
27	no message	bbeaver	8292d 00h	/
26	no message	bbeaver	8292d 23h	/
25	no message	bbeaver	8294d 00h	/
24	no message	bbeaver	8296d 02h	/
23	no message	bbeaver	8297d 01h	/
22	no message	bbeaver	8297d 04h	/
21	Added bookmarks.	lampret	8297d 18h	/
20	Some minor fixes. Document is now official version.	lampret	8297d 18h	/
19	no message	bbeaver	8299d 02h	/
18	no message	bbeaver	8300d 00h	/
17	Fixed link to specification_template.dot	lampret	8300d 08h	/
16	Added updated opencores coding guidelines. Added ver_plan.pdf and Specification template for Word.	lampret	8300d 09h	/
15	no message	bbeaver	8320d 06h	/
14	adding beginning LPM files	bbeaver	8332d 02h	/
13	This commit was manufactured by cvs2svn to create tag 'initial'.		8338d 02h	/