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Subversion Repositories cpu6502_true_cycle

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Rev	Log message	Author	Age	Path
26	v1.4 PRODUCTION	fpga_is_funny	2129d 13h	/
25		fpga_is_funny	2130d 23h	/
24	Bug fix for wrong interrupt sequences in IRQ and NMI. Tested by simulation with RTI and in a real environment by customer. Removed directory ./verilog_TRIAL from source.	fpga_is_funny	5235d 12h	/
23		fpga_is_funny	5235d 13h	/
22		fpga_is_funny	5235d 13h	/
21		fpga_is_funny	5235d 13h	/
20	Added old uploaded documents to new repository.	root	5605d 21h	/
19	Added old uploaded documents to new repository.	root	5606d 14h	/
18	New directory structure.	root	5606d 14h	/
17	CORRECTED "RTI" (wrong: use of stack pointer) RENAME all states of "FSM Execution Unit" for better reading (90%) Finish working for Specification of cpu6502_tc	fpga_is_funny	5618d 16h	/
16	CORRECTED "RTI" (wrong: use of stack pointer) RENAME all states of "FSM Execution Unit" for better reading (90%) Finish working for Specification of cpu6502_tc	fpga_is_funny	5618d 16h	/
15	CORRECTED "RTI" (wrong: use of stack pointer) RENAME all states of "FSM Execution Unit" for better reading (90%) Finish working for Specification of cpu6502_tc	fpga_is_funny	5618d 16h	/
14	More optimizations... - Second Phaze of removing unused nets & registers - Added Verilog source on demand by some customers (for trial use)	fpga_is_funny	5665d 13h	/
13	DELETED directory cpu6502_true_cycle/doc/HTML - use the HTML.RAR file instead	fpga_is_funny	5670d 10h	/
12	no message	fpga_is_funny	5670d 10h	/
11	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead of $02FF and $0300)	fpga_is_funny	5670d 12h	/
10	This commit was manufactured by cvs2svn to create tag 'arelease'.		5670d 12h	/
9	This commit was generated by cvs2svn to compensate for changes in r8, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5670d 12h	/
8	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP JMP (indirect) produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead of $02FF and $0300)	fpga_is_funny	5670d 12h	/
7	This commit was generated by cvs2svn to compensate for changes in r6, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5670d 13h	/
6	* EMERGENCY BUGFIX * - Signal rd_o was corrupted in last version. wr_o and wr_n are not effected. - OP "JMP (indirect)" produced a 65C02 like jump. On 6502 a special case exist when the (indirect) address cross the page boundary (e.g. JMP (02FF) reads from $02FF and $0200, instead $02FF and $0300)	fpga_is_funny	5670d 13h	/
5	Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned.	fpga_is_funny	5932d 15h	/
4	Corrected HTML files for documentation (change $log$ to $Log$ in all VHDL files in first release)	fpga_is_funny	5941d 13h	/
3	This commit was generated by cvs2svn to compensate for changes in r2, which included commits to RCS files with non-trunk default branches.	fpga_is_funny	5941d 14h	/
2	First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now.	fpga_is_funny	5941d 14h	/
1	Standard project directories initialized by cvs2svn.		5941d 14h	/

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Subversion Repositories cpu6502_true_cycle

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