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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4704d 16h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4704d 16h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4704d 18h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4704d 19h /
354 Whitespace cleanup olof 4704d 19h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4706d 21h /
352 Removed delayed assignments from rtl code olof 4711d 02h /
351 Turn defines into parameters in eth_cop olof 4719d 16h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4719d 17h /
349 Make all parameters configurable from top level olof 4720d 18h /
348 Added option to dump VCD files olof 4721d 17h /
347 Added information about running with Icarus Verilog olof 4721d 17h /
346 Updated project location olof 4721d 19h /
345 Temporarily disable failing tests olof 4721d 21h /
344 bit 9 in phy control register is self clearing olof 4727d 23h /
343 Address miss should not be asserted on short frames olof 4731d 19h /
342 Added cast to avoid inequality when comparing different data types olof 4731d 19h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4731d 19h /
340 Don't fail if log dir already exists olof 4732d 17h /
339 Added basic support for Icarus Verilog olof 4733d 16h /
338 root 5525d 22h /
337 root 5582d 00h /
336 Added old uploaded documents to new repository. root 5583d 03h /
335 New directory structure. root 5583d 03h /
334 Minor fixes for Icarus simulator. igorm 7031d 05h /
333 Some small fixes + some troubles fixed. igorm 7031d 17h /
332 Case statement improved for synthesys. igorm 7044d 22h /
331 Tests for delayed CRC and defer indication added. igorm 7060d 00h /
330 Warning fixes. igorm 7060d 00h /
329 Defer indication fixed. igorm 7060d 01h /

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