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Rev Log message Author Age Path
363 quartus project files unneback 4697d 15h /
362 added Makefiles to build project unneback 4697d 15h /
361 created branch unneback unneback 4697d 15h /
360 Added partial implementation of the debug register from ORPSoC olof 4698d 14h /
359 Verilator linting fixes olof 4700d 16h /
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4702d 06h /
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4702d 06h /
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4702d 08h /
355 Import Julius Baxter's verilator hints from ORPSoC olof 4702d 09h /
354 Whitespace cleanup olof 4702d 09h /
353 Inherit fixes for bit width of constants from ORPSoC olof 4704d 11h /
352 Removed delayed assignments from rtl code olof 4708d 16h /
351 Turn defines into parameters in eth_cop olof 4717d 06h /
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4717d 07h /
349 Make all parameters configurable from top level olof 4718d 07h /
348 Added option to dump VCD files olof 4719d 06h /
347 Added information about running with Icarus Verilog olof 4719d 07h /
346 Updated project location olof 4719d 09h /
345 Temporarily disable failing tests olof 4719d 11h /
344 bit 9 in phy control register is self clearing olof 4725d 13h /
343 Address miss should not be asserted on short frames olof 4729d 09h /
342 Added cast to avoid inequality when comparing different data types olof 4729d 09h /
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4729d 09h /
340 Don't fail if log dir already exists olof 4730d 06h /
339 Added basic support for Icarus Verilog olof 4731d 06h /
338 root 5523d 12h /
337 root 5579d 13h /
336 Added old uploaded documents to new repository. root 5580d 17h /
335 New directory structure. root 5580d 17h /
334 Minor fixes for Icarus simulator. igorm 7028d 19h /

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