Rev |
Log message |
Author |
Age |
Path |
64 |
firmware makefiles:
-every firmware makefile has now complete dependency. This also includes dependency on files under minsoc/backend (target specific files). That means, that if some target specific header changes, the support library dependent on it will be compiled. That will always happen, even if you compile the uart firmware. In other words, if you want to use uart firmware, you can always simply compile uart by issuing make all. If anything has changed, backend files, support library, drivers, it will update everything for you.
-TODO: dependency can be automatic created by using make together with gcc. Use it instead of declaring all dependencies manually.
Makefile system for synthesis:
-the dependency for every implementation step has been checked and is working fine.
-Makefile plus support files have been moved to minsoc/syn/src
-make usage is still under syn through files generated by backend bashscripts
Backend:
-files under backend are target specific files used for the system to work
-firmware compilation
-system simulation
-system implementation
-This directory is populated by visiting one of its subdirectories and typing ./configure
backend/spartan3a_dsp_kit:
-working on FPGA
backend/spartan3e_starter_kit:
-has to be tested
backend/ml509:
-missing files have to be copied and adapted, configure script has to be copied and adapted
backend/std:
-include files necessary for firmware compilation and system configuration
-it does not include files for synthesis and is not synthesizable |
rfajardo |
4873d 10h |
/ |
63 |
Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something. |
rfajardo |
4877d 03h |
/ |
62 |
Wrapping different family modules of same manufacturer in a single module.
minsoc_clock_manager.v: uses fpga manufacturer wrappers
xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module
altera_pll.v: selects between different Altera FPGA families and implements the module |
rfajardo |
4877d 10h |
/ |
61 |
Removing supposely defined external function, which don't exist anymore. |
rfajardo |
4877d 11h |
/ |
60 |
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.
minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition. |
rfajardo |
4877d 22h |
/ |
59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4877d 23h |
/ |
58 |
Standard definitions depended on implementation order. Now, this should be solved.
minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.
minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.
IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified. |
rfajardo |
4877d 23h |
/ |
57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4877d 23h |
/ |
56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4884d 22h |
/ |
55 |
Adjusting Makefiles to compile correctly with new firmware updates.
1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere |
rfajardo |
4886d 06h |
/ |
54 |
Moving spr_defs.h to or1200.h |
ConX. |
4886d 08h |
/ |
53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4886d 09h |
/ |
52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4895d 00h |
/ |
51 |
sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) |
rfajardo |
4901d 12h |
/ |
50 |
Removing unused firmware files, respective to or1ksim actually.
Removing the inclusion of the removed file mc.h in reset.S, probably required by or1ksim at some point.
Reworked except.S to use a macro instead of repeating the same procedure 16 times or so. Explanation added to the macro as a leading comment. |
rfajardo |
4913d 09h |
/ |
49 |
Language correction for README.txt. |
rfajardo |
4915d 06h |
/ |
48 |
Clear some old docs that are already ported to MinSOC's Wiki |
ConX. |
4915d 07h |
/ |
47 |
Firmware updated to work with gcc-4.5. It is actually working just fine and gcc-4.5 assembly code seems a lot cleaner.
I noticed that by increasing the free stack space for the interrupt handler by 130 made the resulting firmware not work. I assume it is because 130 is not aligned 130%4 = 2 and the stack simply does not work then. Instead I'm freeing the previous 116 plus 128 (for 32 registers as mentioned by Jeremy) and it works. |
rfajardo |
4916d 06h |
/ |
46 |
Including an explanation of what has to be updated on gpio to port it smoothly to minsoc. |
rfajardo |
4916d 10h |
/ |
45 |
A more stable version |
ConX. |
4917d 01h |
/ |
44 |
Fixing some bugs. But it still works only in Debian/Ubuntu |
ConX. |
4917d 03h |
/ |
43 |
Making some changes to MinSOC install script |
ConX. |
4917d 23h |
/ |
42 |
Tagging release 0.9 of MinSoC. |
rfajardo |
4922d 06h |
/ |
41 |
Including setup scripts to install all required tools to work with minsoc and to download all required sources. Thanks for the contribution of Xanthopoulos Constantinos. |
rfajardo |
4922d 06h |
/ |
40 |
Commiting a contributions directory, which has raw contributions of users. These contributions still have to be adapted to the system in order to work well. However, some users are certainly able to work with these versions.
FAQ: -added new idea to circumvent onboard DLC9 cable problem for adv_jtag_bridge
INSTALL: -gives a hint on how to install the system for Windows
HOWTO: -explains what a ucf file is and how to create it
backend: now we have the first contribution of a ucf file for the ML509 board (thanks to Matthew Hick)
Documentation: THESIS.txt explains to users, willing to tweak/understand the inner behavior of the OR1200 implementation of OpenRISC, what to read in order to get this information. |
rfajardo |
4928d 05h |
/ |
39 |
FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes
Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed. |
rfajardo |
4992d 22h |
/ |
38 |
Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-).
FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset.
uart.c: now uses the IRQ line definition instead of the line number directly. |
rfajardo |
5027d 21h |
/ |
37 |
README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next.
Clean-up of sw/utils, removing unused sources and files.
Update of sw/drivers/eth.c, direct casting to avoid compile warnings.
FAQ extended and with more links to the threads giving the solutions.
Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35.
minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better. |
rfajardo |
5058d 08h |
/ |
36 |
utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect.
-adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess.
sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.
sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores.
sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead.
Documentation:
-FAQ extended:
-table of contents
-explanation of how to use the 32 to 8 bit Wishbone bridge
-how to make adv_jtag_bridge work without privilege requirement for xess or xpc3
-explanation of locking problem of xpc_usb cable
-explanation of what to do if the cable is built on-board
-INSTALL:
-patching of gdb only required if version is 6.8, explanation on FAQ now.
-HOWTO:
-instruct to compile drivers library
-remove line numbers information on what to edit, better leave it to be found only by the informed context.
-adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement. |
rfajardo |
5059d 03h |
/ |
35 |
minsoc.pdf: -adjusting the date on the page header of MinSoC documentation. It was correct on the front and revision pages, now header adjusted accordingly. |
rfajardo |
5063d 21h |
/ |