OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] - Rev 189

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
189 fixed mode handling for tick facility chris 8346d 11h /
188 fixed PIC interrupt controller chris 8346d 11h /
187 minor change to clear pending exception chris 8346d 11h /
186 major change to UART structure chris 8346d 11h /
185 major change to UART code chris 8346d 11h /
184 modified decode for trace debugging chris 8346d 11h /
183 changed special case for PICSR chris 8346d 11h /
182 updated exception handling procedures chris 8346d 11h /
181 Added trace/stall commands chris 8346d 12h /
180 Updated debug. lampret 8346d 17h /
179 Sim run script lampret 8366d 10h /
178 Some test code lampret 8366d 10h /
177 Improved wb_sram model lampret 8366d 10h /
176 IC enable/disable. lampret 8366d 10h /
175 Added new configure option --enable-impl=[default,mp3,bender],
which defines IMPL_impl.
It selects implementation specific environment. One should
#ifdef the code that is different than default.		 markom 8367d 05h /
174 Few changes that should be done previously:
- machine.h replaced by spr_defs.h
- if reset label does not exist, boot from 0x0100		 markom 8367d 08h /
173 - profiler added, use e.g.:
make profiler
./sim -profile -fast executable
./profiler -g [-c]

(no special compiling options necessary)		 markom 8369d 12h /
172 Removing obsolete files. lampret 8370d 14h /
171 Added monitor.v and timescale.v lampret 8370d 14h /
170 Added cfg regs. Moved all defines into one defines.v file. More cleanup. lampret 8370d 14h /
169 Fixed memory cells. Moved monitor.h into monitor.v lampret 8370d 14h /
168 Major clean-up. lampret 8374d 04h /
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8375d 04h /
166 Fixed RAM's oen bug. Cache bypass under development. lampret 8392d 14h /
165 Added variable ack of WB transfers (see NODELAY_WBx). lampret 8392d 14h /
164 *** empty log message *** lampret 8394d 17h /
163 Forgot files.f file. lampret 8394d 17h /
162 Benches (under development). lampret 8394d 17h /
161 Development version of RTL. Libraries are missing. lampret 8394d 17h /
160 simulation script lampret 8394d 17h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.