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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7972d 15h /
67 Changed BIST signals for RAMs. tadejm 7972d 20h /
66 Changed empty status generation in pciw_fifo_control.v mihad 7976d 06h /
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7979d 04h /
64 The testcase I just added in previous revision repaired mihad 7979d 06h /
63 Added additional testcase and changed rst name in BIST to trst mihad 7979d 08h /
62 Added BIST signals for RAMs. mihad 7982d 01h /
61 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7990d 01h /
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7990d 01h /
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 02h /
58 Removed all logic from asynchronous reset network mihad 7995d 03h /
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7995d 09h /
56 Number of state bits define was removed mihad 7995d 23h /
55 Changed state machine encoding to true one-hot mihad 7996d 00h /
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8029d 02h /
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8029d 05h /
52 Oops, never before noticed that OC header is missing mihad 8029d 09h /
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8029d 09h /
50 Got rid of undef directives mihad 8032d 02h /
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8032d 02h /
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8032d 02h /
47 Known issues repaired mihad 8032d 07h /
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8037d 02h /
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8038d 07h /
44 Added for testing of Configuration Cycles Type 1 mihad 8038d 08h /
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8038d 08h /
42 Removed out of date files mihad 8050d 08h /
41 This commit was manufactured by cvs2svn to create tag 'rel_00'. 8128d 23h /
40 From these Wrod files PDF were created - added future improvements tadej 8128d 23h /
39 File not needed tadej 8129d 00h /

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