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Subversion Repositories simple_fm_receiver

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Rev	Log message	Author	Age	Path
32	New directory structure.	root	5588d 09h	/
31	Include flattening process, simplify build system.	arif_endro	5800d 09h	/
30	Clean up.	arif_endro	5844d 14h	/
29	Done fixing Makefile for Alliance.	arif_endro	5844d 14h	/
28	chip IO place.	arif_endro	5845d 10h	/
27	chip IO interface.	arif_endro	5845d 10h	/
26	Removed.	arif_endro	5845d 10h	/
25	IO place.	arif_endro	5845d 10h	/
24	Update to use Alliance CAD System by ASIM/LIP6/UMPC	arif_endro	5845d 12h	/
23	Disable clear signal.	arif_endro	5845d 12h	/
22	Update last bit output assignment method.	arif_endro	5845d 12h	/
21	This commit was manufactured by cvs2svn to create tag 'version_1_1'.		7030d 13h	/
20	New Version	arif_endro	7030d 13h	/
19	Screen shot from chipscope analyzer view, this is how this design work.	arif_endro	7036d 12h	/
18	This bit files generates better wave than previous (i.e. more smooth)	arif_endro	7036d 14h	/
17	Initial Checkin	arif_endro	7044d 11h	/
16	Changes constan and minor fix	arif_endro	7047d 14h	/
15	Xilinx FPGA XC2V2000 bit files the first version.	arif_endro	7050d 12h	/
14	* empty log message *	arif_endro	7055d 10h	/
13	Update License	arif_endro	7066d 11h	/
12	Update License Change reset signal handle	arif_endro	7066d 12h	/
11	Update License Change reset signal handle	arif_endro	7066d 12h	/
10	Added script for generating cos ROM.	arif_endro	7076d 15h	/
9	Added documentation	arif_endro	7093d 14h	/
8	This commit was manufactured by cvs2svn to create tag 'okinawa_1'.		7107d 14h	/
7	To view chipscope exported output using ModelSim waveform window	arif_endro	7107d 14h	/
6	Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO)	arif_endro	7108d 16h	/
5	Added interface in/out and testing paralelly (e.g. square and triangular)	arif_endro	7108d 16h	/
4	Fix elsif and if statement	arif_endro	7111d 10h	/
3	This commit was manufactured by cvs2svn to create tag 'VSFR_1'.		7114d 16h	/

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