URL https://opencores.org/ocsvn/t51/t51/trunk

Subversion Repositories t51

[/] - Rev 48

Rev	Log message	Author	Age	Path
48	* empty log message *	andreas	6616d 00h	/
47	updated t8052 core	andreas	6616d 06h	/
46	some updates	andreas	6616d 06h	/
45	* empty log message *	andreas	6616d 06h	/
44	some updates and bugfixes	andreas	6616d 06h	/
43	bugfix for interrupts at stalled instructions	andreas	6699d 00h	/
42	* empty log message *	andreas	6717d 23h	/
41	some updates	andreas	6717d 23h	/
40	* empty log message *	andreas	6717d 23h	/
39	some updates for T8032	andreas	6717d 23h	/
38	some updates	andreas	6727d 07h	/
37	some updates	andreas	6727d 07h	/
36	some updates	andreas	6727d 10h	/
35	some updates	andreas	6727d 10h	/
34	bugfix for mode 0	andreas	6736d 02h	/
33	bugfix for JBC instruction	andreas	6748d 08h	/
32	bugfix for two subsequent movx instructions	andreas	6785d 02h	/
31	update	andreas	6871d 01h	/
30	Made some bugfixes	andreas	6872d 05h	/
29	Removed UNISIM library	jesus	7882d 08h	/
28	Added -n option and component declaration	jesus	7910d 05h	/
27	Added Leonardo .ucf generation	jesus	7910d 05h	/
26	Updated for ISE 5.1	jesus	7917d 02h	/
25	Fixed typo	jesus	7926d 17h	/
24	Fixed for ISE 5.1	jesus	7926d 17h	/
23	Xilinx SSRAM, initial release	jesus	7936d 19h	/
22	Removed write through	jesus	7964d 16h	/
21	no message	jesus	7964d 20h	/
20	Added support for XST	jesus	7991d 08h	/
19	Updated for wishbone	jesus	8059d 21h	/