URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 114

Rev	Log message	Author	Age	Path
114	remove t2mod register	simont	7785d 08h	/
113	signal prsc_ow added.	simont	7785d 08h	/
112	change timers to meet timing specifications (add divider with 12)	simont	7785d 08h	/
111	Remove instruction cache and wb_interface	simont	7785d 23h	/
110	change adr_i and adr_o length.	simont	7785d 23h	/
109	add `include "oc8051_defines.v"	simont	7785d 23h	/
108	fix some bugs, use oc8051_cache_ram.	simont	7785d 23h	/
107	Include instruction cache.	simont	7785d 23h	/
106	generic_dpram used	simont	7787d 02h	/
105	generic_dpram used	simont	7787d 02h	/
104	use generic_dpram	simont	7787d 02h	/
103	rename signals	simont	7787d 03h	/
102	raname signals.	simont	7787d 03h	/
101	initial inport	simont	7787d 06h	/
100	use \	simont	7787d 07h	/
99	change directory structure	simont	7787d 07h	/
98	move to rtl/verilog	simont	7787d 07h	/
97	initial inport	simont	7787d 07h	/
96	initial import	simont	7787d 07h	/
95	updating...	simont	7787d 07h	/
94	fix bug.	simont	7787d 07h	/
93	OC8051_XILINX_RAM added	simont	7787d 07h	/
92	initial inport	simont	7787d 07h	/
91	* empty log message *	simont	7787d 07h	/
90	change module name.	simont	7792d 01h	/
89	Replaced oc8051_ram by generic_dpram.	rherveille	7853d 04h	/
88	fix bugs	simont	7858d 04h	/
87	add include oc8051_defines.v	simont	7858d 05h	/
86	initial input	simont	7858d 05h	/
85	prepare bugs	simont	7858d 05h	/