URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 132

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Rev	Log message	Author	Age	Path
132	change branch instruction execution (reduse needed clock periods).	simont	7768d 03h	/
131	prepare programs for new timing.	simont	7768d 03h	/
130	prepared programs for new timing.	simont	7768d 03h	/
129	updated...	simont	7768d 03h	/
128	chance idat_ir to 24 bit wide	simont	7777d 10h	/
127	fix bug (cyc_o and stb_o)	simont	7777d 10h	/
126	define OC8051_XILINX_RAMB added	simont	7777d 10h	/
125	update, add prescaler, rclk, tclk.	simont	7777d 10h	/
124	add support for external rom from xilinx ramb4	simont	7777d 10h	/
123	fiz bug iv pcs operation.	simont	7779d 06h	/
122	deifne OC8051_ROM added	simont	7782d 10h	/
121	Change pc add value from 23'h to 16'h	simont	7782d 10h	/
120	defines for pherypherals added	simont	7783d 07h	/
119	remove signal sbuf_txd [12:11]	simont	7783d 11h	/
118	change wr_sft to 2 bit wire.	simont	7784d 04h	/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7784d 04h	/
116	change sfr's interface.	simont	7786d 05h	/
115	change uart to meet timing.	simont	7786d 07h	/
114	remove t2mod register	simont	7789d 10h	/
113	signal prsc_ow added.	simont	7789d 10h	/
112	change timers to meet timing specifications (add divider with 12)	simont	7789d 10h	/
111	Remove instruction cache and wb_interface	simont	7790d 01h	/
110	change adr_i and adr_o length.	simont	7790d 01h	/
109	add `include "oc8051_defines.v"	simont	7790d 01h	/
108	fix some bugs, use oc8051_cache_ram.	simont	7790d 01h	/
107	Include instruction cache.	simont	7790d 01h	/
106	generic_dpram used	simont	7791d 04h	/
105	generic_dpram used	simont	7791d 04h	/
104	use generic_dpram	simont	7791d 04h	/
103	rename signals	simont	7791d 05h	/

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Subversion Repositories 8051

[/] - Rev 132

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