URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 140

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Rev	Log message	Author	Age	Path
140	cahnge assigment to pc_wait (remove istb_o)	simont	7734d 00h	/
139	add aditional alu destination to solve critical path.	simont	7734d 18h	/
138	Change buffering to save one clock per instruction.	simont	7734d 18h	/
137	change to fit xrom.	simont	7734d 23h	/
136	registering outputs.	simont	7734d 23h	/
135	prepared start of receiving if ren is not active.	simont	7740d 23h	/
134	fix bug in case execution of two data dependent instructions.	simont	7740d 23h	/
133	fix bug in substraction.	simont	7741d 01h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7744d 17h	/
131	prepare programs for new timing.	simont	7744d 17h	/
130	prepared programs for new timing.	simont	7744d 17h	/
129	updated...	simont	7744d 17h	/
128	chance idat_ir to 24 bit wide	simont	7754d 00h	/
127	fix bug (cyc_o and stb_o)	simont	7754d 00h	/
126	define OC8051_XILINX_RAMB added	simont	7754d 00h	/
125	update, add prescaler, rclk, tclk.	simont	7754d 00h	/
124	add support for external rom from xilinx ramb4	simont	7754d 00h	/
123	fiz bug iv pcs operation.	simont	7755d 20h	/
122	deifne OC8051_ROM added	simont	7759d 00h	/
121	Change pc add value from 23'h to 16'h	simont	7759d 00h	/
120	defines for pherypherals added	simont	7759d 21h	/
119	remove signal sbuf_txd [12:11]	simont	7760d 01h	/
118	change wr_sft to 2 bit wire.	simont	7760d 18h	/
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7760d 18h	/
116	change sfr's interface.	simont	7762d 19h	/
115	change uart to meet timing.	simont	7762d 21h	/
114	remove t2mod register	simont	7765d 23h	/
113	signal prsc_ow added.	simont	7765d 23h	/
112	change timers to meet timing specifications (add divider with 12)	simont	7765d 23h	/
111	Remove instruction cache and wb_interface	simont	7766d 15h	/

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Subversion Repositories 8051

[/] - Rev 140

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