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Subversion Repositories 8051

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Rev Log message Author Age Path
151 remove pc_r register. simont 7691d 05h /
150 fix some bugs. simont 7691d 05h /
149 pipelined acces to axternal instruction interface added. simont 7691d 05h /
148 include "8051_defines" added. simont 7691d 05h /
147 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7713d 06h /
146 fix bug in movc intruction. simont 7713d 06h /
145 fix bug in case of sequence of inc dptr instrucitons. simont 7718d 10h /
144 chsnge comp.des to des1 simont 7718d 10h /
143 add wire sub_result, conect it to des_acc and des1. simont 7718d 10h /
142 optimize state machine. simont 7719d 11h /
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7719d 12h /
140 cahnge assigment to pc_wait (remove istb_o) simont 7719d 13h /
139 add aditional alu destination to solve critical path. simont 7720d 06h /
138 Change buffering to save one clock per instruction. simont 7720d 06h /
137 change to fit xrom. simont 7720d 12h /
136 registering outputs. simont 7720d 12h /
135 prepared start of receiving if ren is not active. simont 7726d 11h /
134 fix bug in case execution of two data dependent instructions. simont 7726d 11h /
133 fix bug in substraction. simont 7726d 14h /
132 change branch instruction execution (reduse needed clock periods). simont 7730d 05h /
131 prepare programs for new timing. simont 7730d 05h /
130 prepared programs for new timing. simont 7730d 05h /
129 updated... simont 7730d 05h /
128 chance idat_ir to 24 bit wide simont 7739d 12h /
127 fix bug (cyc_o and stb_o) simont 7739d 12h /
126 define OC8051_XILINX_RAMB added simont 7739d 12h /
125 update, add prescaler, rclk, tclk. simont 7739d 12h /
124 add support for external rom from xilinx ramb4 simont 7739d 12h /
123 fiz bug iv pcs operation. simont 7741d 08h /
122 deifne OC8051_ROM added simont 7744d 12h /

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