URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 160

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Rev	Log message	Author	Age	Path
160	initial inport.	simont	7693d 18h	/
159	initial inport.	simont	7693d 19h	/
158	fix bug.	simont	7693d 19h	/
157	change data output.	simont	7693d 19h	/
156	add FREQ paremeter.	simont	7693d 19h	/
155	add aditional tests.	simont	7693d 19h	/
154	File name fixed.	simont	7694d 14h	/
153	`ifdef added.	simont	7695d 13h	/
152	sub_result output added.	simont	7695d 13h	/
151	remove pc_r register.	simont	7695d 13h	/
150	fix some bugs.	simont	7695d 13h	/
149	pipelined acces to axternal instruction interface added.	simont	7695d 13h	/
148	include "8051_defines" added.	simont	7695d 13h	/
147	This commit was manufactured by cvs2svn to create tag 'rel_1'.		7717d 14h	/
146	fix bug in movc intruction.	simont	7717d 14h	/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7722d 17h	/
144	chsnge comp.des to des1	simont	7722d 17h	/
143	add wire sub_result, conect it to des_acc and des1.	simont	7722d 17h	/
142	optimize state machine.	simont	7723d 19h	/
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7723d 20h	/
140	cahnge assigment to pc_wait (remove istb_o)	simont	7723d 20h	/
139	add aditional alu destination to solve critical path.	simont	7724d 14h	/
138	Change buffering to save one clock per instruction.	simont	7724d 14h	/
137	change to fit xrom.	simont	7724d 19h	/
136	registering outputs.	simont	7724d 19h	/
135	prepared start of receiving if ren is not active.	simont	7730d 19h	/
134	fix bug in case execution of two data dependent instructions.	simont	7730d 19h	/
133	fix bug in substraction.	simont	7730d 21h	/
132	change branch instruction execution (reduse needed clock periods).	simont	7734d 13h	/
131	prepare programs for new timing.	simont	7734d 13h	/

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Subversion Repositories 8051

[/] - Rev 160

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